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1.发明公开公开(公告)号：US20240120935A1
公开(公告)日：2024-04-11
申请号：US17961845
申请日：2022-10-07
申请人： Ciena Corporation
摘要： A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.
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公开(公告)号：US20180373303A1
公开(公告)日：2018-12-27
申请号：US15631734
申请日：2017-06-23
发明人： Peter Hansen , Julie Victoria Tan
CPC分类号： G06F1/3206 , G06F1/3225 , H03K7/08 , H03M1/001 , H03M1/002 , H03M1/504
摘要： Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.
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公开(公告)号：US20180115318A1
公开(公告)日：2018-04-26
申请号：US15793514
申请日：2017-10-25
CPC分类号： H03M1/1245 , H03M1/504 , H03M3/494
摘要： A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.
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公开(公告)号：US09891593B2
公开(公告)日：2018-02-13
申请号：US15311550
申请日：2015-05-17
CPC分类号： G04F10/005 , H03M1/504
摘要： The present invention relates to the realization of an ADC by using a one shot time cell as an analog-to-time converter and a time-to-digital converter. The present invention relates in general, to the design and Integrated Circuit (IC) implementation of a fully-digital fully-synthesizable, delay-line analog-to-digital converter (DL-ADC). The present invention is specifically relevant for power management applications where the silicon area of the controller is of key importance. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant of the silicon area.
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公开(公告)号：US20170346501A1
公开(公告)日：2017-11-30
申请号：US15663411
申请日：2017-07-28
CPC分类号： H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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公开(公告)号：US20160126968A1
公开(公告)日：2016-05-05
申请号：US14931332
申请日：2015-11-03
CPC分类号： H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
摘要翻译： 本申请涉及模拟 - 数字转换器（ADC）。 ADC200具有第一转换器（201），用于接收模拟输入信号（AIN），并输出诸如脉冲宽度调制（PWM）信号的时间编码信号（DT），其基于输入信号和第一转换 增益设置（GIN）。 在一些实施例中，第一转换器具有用于产生PWM信号的PWM调制器（401），使得输入信号由可在时间上连续变化的脉冲宽度编码。 第二转换器（202）接收时间编码信号并基于时间编码信号（DT）和第二转换增益设置（GO）输出数字输出信号（DOUT）。 第二转换器可以具有第一PWM到数字调制器（403）。 增益分配块（204）基于时间编码信号（DT）生成第一和第二转换增益设置。 增益分配块（204）可以具有第二PWM到数字调制器（203），其可以具有第一PWM到数字调制器（403）的较低等待时间和/或更低的分辨率。
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公开(公告)号：US08830104B2
公开(公告)日：2014-09-09
申请号：US13187975
申请日：2011-07-21
IPC分类号： H03M1/12
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译： 公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。
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公开(公告)号：US20110290987A1
公开(公告)日：2011-12-01
申请号：US13116052
申请日：2011-05-26
申请人： MING-HUANG LIU , MENG-YUNG LIN
发明人： MING-HUANG LIU , MENG-YUNG LIN
CPC分类号： G01J1/46 , G01J1/4204 , H03K4/50 , H03K7/08 , H03M1/504
摘要： The present invention provides an ambient light sensing module, which comprises a sawtooth signal generating circuit, an optical sensing unit, and a comparing unit. The sawtooth signal generating circuit produces a sawtooth signal. The optical sensing unit senses a light source and produces a light-sensing signal. The comparing unit produces a pulse-width modulation (PWM) signal related to the intensity of the light source according to the light-sensing signal and the sawtooth signal so that the PWM signal can be used as the control signal of the electronic device. The ambient light sensing module further comprises at least a fuse for determining a processing parameter. A signal processing unit processes the light-sensing signal according to the processing parameter for outputting a converting signal. The comparing unit compares the converting signal with the sawtooth signal for producing the PWM signal. An adjusting unit produces an adjusting signal according to the PWM signal and the light intensity or according to the converting signal and the light intensity for controlling a trimming unit to trim the fuse and thus modifying the processing parameter.
摘要翻译： 本发明提供一种环境光感测模块，其包括锯齿波信号发生电路，光学感测单元和比较单元。 锯齿波信号产生电路产生锯齿波信号。 光学感测单元感测光源并产生光感测信号。 比较单元根据光感测信号和锯齿波信号产生与光源的强度相关的脉冲宽度调制（PWM）信号，使得PWM信号可以用作电子设备的控制信号。 环境光感测模块还包括用于确定处理参数的至少一个熔丝。 信号处理单元根据用于输出转换信号的处理参数对感光信号进行处理。 比较单元将转换信号与锯齿波信号进行比较，以产生PWM信号。 调整单元根据PWM信号和光强度或根据转换信号和光强度产生调节信号，用于控制修整单元以修整熔丝并因此修改处理参数。
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9.发明授权公开(公告)号：US07782241B2
公开(公告)日：2010-08-24
申请号：US12187773
申请日：2008-08-07
申请人： Masahiro Kudo , Hiroshi Yamazaki
发明人： Masahiro Kudo , Hiroshi Yamazaki
IPC分类号： H03M1/60
CPC分类号： H03M1/504
摘要： The first and second time-domain signals are received, and a difference between the pulse width of the first time-domain signal and the pulse width of the second time-domain signal within a unit time for carrying one item of analog signal information is obtained. The obtained difference is treated as positive information if the pulse width of the first time-domain signal is greater than the pulse width of the second time-domain signal, or as negative information if the pulse width of the first time-domain signal is smaller than the pulse width of the second time-domain signal.
摘要翻译： 接收第一和第二时域信号，并且获得用于携带一个模拟信号信息的单位时间内的第一时域信号的脉冲宽度与第二时域信号的脉冲宽度之间的差 。 如果第一时域信号的脉冲宽度大于第二时域信号的脉冲宽度，则获得的差值被视为正信息，或者如果第一时域信号的脉冲宽度较小，则将其作为负信息 比第二时域信号的脉冲宽度。
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公开(公告)号：US07777656B2
公开(公告)日：2010-08-17
申请号：US11749191
申请日：2007-05-16
IPC分类号： H03M3/00
摘要： Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.
摘要翻译： 描述和描述了解码器，编码器/解码器系统和转换器的实现和实施例。
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