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公开(公告)号：US09628101B1
公开(公告)日：2017-04-18
申请号：US15276943
申请日：2016-09-27
发明人： Akinobu Onishi
CPC分类号： H03M3/464 , H03M1/12 , H03M1/1245 , H03M1/183 , H03M1/185 , H03M1/46 , H03M3/422 , H03M3/452 , H03M3/484
摘要： Various embodiments of the present technology may comprise a method and apparatus for an analog-to digital converter (ADC). Methods and apparatus for an ADC according to various aspects of the present invention may operate in conjunction with a reference voltage that varies according to the frequency of a timing signal. By varying the reference voltage according to the frequency of the timing signal, the ADC generates a digital output having a substantially fixed voltage variation regardless of the frequency of the timing signal.
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公开(公告)号：US20160359500A1
公开(公告)日：2016-12-08
申请号：US15243305
申请日：2016-08-22
IPC分类号： H03M7/30
CPC分类号： H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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3.发明授权Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters 有权用于在增量式Δ-Σ模数转换器中设置输出信号的有效分辨率的方法和装置公开(公告)号：US09379734B2
公开(公告)日：2016-06-28
申请号：US14939679
申请日：2015-11-12
发明人： Raik Richter , Marko Mailand
IPC分类号： H03M3/00
摘要： A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.
摘要翻译： 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对于大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。
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公开(公告)号：US20120007760A1
公开(公告)日：2012-01-12
申请号：US13242719
申请日：2011-09-23
申请人： Niels Ole KNUDSEN
发明人： Niels Ole KNUDSEN
摘要： In order to minimize noise and current consumption in a hearing aid, an input converter comprising a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.
摘要翻译： 为了最小化助听器中的噪声和电流消耗，设计了一种包括第一电压互感器和用于助听器的delta-sigma类型的模 - 数转换器的输入转换器。 输入转换器的模数转换器具有输入级，输出级和反馈回路，输入级包括放大器（QA）和积分器（RLF）。 第一变压器（IT）具有变压比，使得它提供大于输入电压的输出电压，并被放置在输入转换器的上游输入级。 具有变压比使得其提供大于输入电压的输出电压的第二变压器（OT）可选地放置在转换器的反馈环路中。 电压互感器（IT，OT）是开关电容器电压互感器，每个变压器（IT，OT）具有至少两个电容器（Ca，Cb，Cc，Cd）。 本发明还提供一种转换模拟信号的方法。
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公开(公告)号：US07453382B2
公开(公告)日：2008-11-18
申请号：US11651925
申请日：2007-01-10
IPC分类号： H03M3/00
摘要： A method and an apparatus for converting an analog input signal into a digital output signal using a sigma-delta modulator architecture with a digital tracking filter. The digital tracking filter may have and order greater than one, and the signal and noise transfer functions of the sigma-delta modulator architecture are chosen to provide a sigma-delta modulator architecture with a high dynamic range even if a relatively low oversampling ratio is used.
摘要翻译： 一种使用具有数字跟踪滤波器的Σ-Δ调制器架构将模拟输入信号转换为数字输出信号的方法和装置。 数字跟踪滤波器可以具有大于1的数量跟踪滤波器，并且选择Σ-Δ调制器架构的信号和噪声传递函数以提供具有高动态范围的Σ-Δ调制器架构，即使使用相对较低的过采样比 。
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公开(公告)号：US20080018509A1
公开(公告)日：2008-01-24
申请号：US11761746
申请日：2007-06-12
申请人： Morgan Colmer
发明人： Morgan Colmer
IPC分类号： H03M3/02
摘要： A sigma-delta modulator for forming a digital output signal representative of the magnitude of an analog input signal, the modulator comprising a modulation unit comprising: a summation unit for summing the analog input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; and a quantizer arranged to receive the integrator output signal and form the digital output signal dependent thereon; the sigma-delta modulator further comprising a feedback loop for generating the adjustment signal and comprising a selection circuit arranged to form the adjustment signal by selecting between one of two boundary values for the adjustment signal, the selection being performed in dependence on the digital output signal.
摘要翻译： 一种用于形成表示模拟输入信号幅度的数字输出信号的Σ-Δ调制器，所述调制器包括：调制单元，包括：求和单元，用于将所述模拟输入信号与调整信号相加以形成求和输出信号; 积分器，被布置成接收所述求和输出信号并形成依赖于其的积分器输出信号; 以及量化器，被布置成接收积分器输出信号并形成依赖于其的数字输出信号; 所述Σ-Δ调制器还包括用于产生所述调整信号的反馈回路，并且包括选择电路，所述选择电路经布置以通过在所述调整信号的两个边界值中的一个之间进行选择来形成所述调整信号，所述选择根据所述数字输出信号 。
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7.发明申请Analog-to-digital-converter comprising a sigma-delta-modulator and receiver with such analog-to-digital-converter 审中-公开包括具有这种模数转换器的Σ-Δ调制器和接收器的模数转换器公开(公告)号：US20060164272A1
公开(公告)日：2006-07-27
申请号：US10562272
申请日：2004-06-24
IPC分类号： H03M3/00
摘要： Analog-to-digital converter including a sigma-delta modulator (SD) with noise shaping filtering. Signal transfer filtering is introduced in the feedback loop of the sigma-delta modulator. This may be done without affecting the noise shaping filtering e.g. with a signal transfer filter (L) in the forward path of the feedback loop and a complementary signal transfer path (H) in the feedback path of the loop. The analog-to-digital converter may be used for channel filtering, FM-demodulation and/or image rejection in communication receivers.
摘要翻译： 模数转换器包括具有噪声整形滤波的Σ-Δ调制器（SD）。 在Σ-Δ调制器的反馈环路中引入信号传输滤波。 这可以在不影响噪声整形滤波的情况下完成。 在反馈环路的正向路径中具有信号传输滤波器（L），并且在环路的反馈路径中具有互补信号传送路径（H）。 模数转换器可用于通信接收机中的信道滤波，FM解调和/或镜像抑制。
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8.发明申请公开(公告)号：US20050179487A1
公开(公告)日：2005-08-18
申请号：US10780188
申请日：2004-02-17
申请人： Wai Lee , Shawn Stapleton , Kelly Mekechuk
发明人： Wai Lee , Shawn Stapleton , Kelly Mekechuk
CPC分类号： H03F3/217 , H03F2200/111 , H03F2200/331 , H03F2200/451 , H03M3/41 , H03M3/484 , H03M3/49
摘要： A radio frequency (RF) switching power amplifier comprises: a switching amplifier 203 to provide an amplified signal within an RF band; and a delta signal modulator (DSM) 207 that is operable; to control the switching amplifier in a feedback configuration, to process an input signal within an intermediate frequency (IF) band where the input signal corresponds to a base band signal and the amplified signal, and to provide an output signal within the RF band to drive the switching amplifier. Certain embodiments allow for or compensate for a floating or variable IF band and multiple RF bands.
摘要翻译： 射频（RF）开关功率放大器包括：开关放大器203，用于在RF频带内提供放大的信号; 和可操作的Δ信号调制器（DSM）207; 以在反馈配置中控制开关放大器，以处理中频（IF）频带内的输入信号，其中输入信号对应于基带信号和放大信号，并且在RF频带内提供输出信号以驱动 开关放大器。 某些实施例允许或补偿浮动或可变IF频带和多个RF频带。
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9.发明公开公开(公告)号：US20240106455A1
公开(公告)日：2024-03-28
申请号：US17950486
申请日：2022-09-22
申请人： NXP B.V.
发明人： Dave Sebastiaan Kroekenstoel , Muhammad Kamran , Harry Neuteboom , Costantino Ligouras , Sergio Andrés Rueda Gómez
摘要： Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.
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公开(公告)号：US20170346501A1
公开(公告)日：2017-11-30
申请号：US15663411
申请日：2017-07-28
CPC分类号： H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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