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公开(公告)号：US11996866B2
公开(公告)日：2024-05-28
申请号：US18178552
申请日：2023-03-06
Applicant: xMEMS Labs, Inc.
Inventor： Jemm Yue Liang , Hsi-Sheng Chen , Chieh-Yao Chang , Hung-Chi Huang , Jing-Meng Liu
IPC: H03M3/00
Abstract: A feedback control system configured to drive a load is disclosed. The feedback control system includes an up-sampling circuit, configured to perform an un-sampling operation on a source signal and produce an up-sampled signal with an up-sampling frequency according to the up-sampled signal and a feedback signal from the load; a delta circuit, coupled to the up-sampling circuit and configured to produce a delta signal; a sigma circuit, configured to produce a density modulation signal according to the delta signal; and a driving device, configured to drive the load according to the density modulation signal with the up-sampling frequency.
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公开(公告)号：US20180310087A1
公开(公告)日：2018-10-25
申请号：US15493252
申请日：2017-04-21
Applicant: Infineon Technologies Austria AG
Inventor： Cesare BUFFA , Fernando CARDES GARCIA , Luis HERNANDEZ-CORPORALES , Bernhard KUTTIN , Andres QUINTERO ALONSO , Andreas WIESBAUER
CPC classification number: H04R1/04 , H03K3/0315 , H03M3/454 , H04R19/005 , H04R19/04
Abstract: In various embodiments, a circuit is provided. The circuit includes: a voltage biasing circuit coupled to a microelectro-mechanical system (MEMS) microphone sensor, the MEMS microphone sensor coupled to a driver circuit, and the driver circuit coupled to an oscillator-based ADC circuit. The oscillator-based ADC circuit may include an Nth order sigma-delta modulator, where N is an integer equal to or greater than 1.
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公开(公告)号：US09871533B2
公开(公告)日：2018-01-16
申请号：US15421989
申请日：2017-02-01
Applicant: Infineon Technologies AG
Inventor： Igor Ullmann
Abstract: An analog/digital converter (ADC) includes an analog stage with at least one first sigma-delta modulator and includes a digital stage with at least one second sigma-delta modulator. The analog stage is configured for outputting a digital signal to the digital stage that is indicative of a noise contribution of the at least one first sigma-delta modulator. The analog stage and the digital stage may be arranged in a multi-stage noise shaping architecture (MASH) architecture.
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公开(公告)号：US09859914B1
公开(公告)日：2018-01-02
申请号：US15647253
申请日：2017-07-11
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
CPC classification number: H03M3/426 , H03M1/00 , H03M1/066 , H03M1/12 , H03M3/30 , H03M3/428 , H03M3/436 , H03M3/454
Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.
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公开(公告)号：US09859855B2
公开(公告)日：2018-01-02
申请号：US15079256
申请日：2016-03-24
Inventor： Martin Kinyua , Eric Soenen
CPC classification number: H03F3/2178 , H02M1/12 , H03F3/183 , H03F3/2175 , H03F2200/03 , H03F2200/135 , H03F2200/165 , H03M1/12 , H03M1/747 , H03M3/434 , H03M3/454 , H03M3/458
Abstract: A Class-D amplifier includes an analog-to-digital converter (ADC) having a first input node. The ADC receives a first analog input signal and a first feedback signal at the first input node and generates a first digital signal based on the first analog input signal and the first feedback signal. A digital filter generates a second digital signal based on the first digital signal. An output circuit includes a first output node, the output circuit being configured to generate a first output signal at the first output node based on the second digital signal. A first feedback unit generates the first feedback signal as the first output signal scaled by a gain factor having a constant value in the Z-domain.
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Patent Agency Ranking
公开(公告)号：US09825645B1
公开(公告)日：2017-11-21
申请号：US15389297
申请日：2016-12-22
Applicant: Infineon Technologies AG
Inventor： Richard Gaggl , Enrique Prefasi , Francisco Javier Perez Sanjurjo , Cesare Buffa
CPC classification number: H03M3/422 , H03M1/00 , H03M1/0624 , H03M1/12 , H03M1/52 , H03M3/30 , H03M3/454 , H03M3/46 , H03M2201/4233
Abstract: The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.
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公开(公告)号：US09735801B1
公开(公告)日：2017-08-15
申请号：US15403683
申请日：2017-01-11
Applicant: Takashi Miki
Inventor： Takashi Miki
IPC: H03M3/00
Abstract: A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.
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公开(公告)号：US20170214412A1
公开(公告)日：2017-07-27
申请号：US15403683
申请日：2017-01-11
Applicant: Takashi MIKI
Inventor： Takashi MIKI
IPC: H03M3/00
Abstract: A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.
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公开(公告)号：US09712184B2
公开(公告)日：2017-07-18
申请号：US15197398
申请日：2016-06-29
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
Abstract: A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
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10.发明授权Suppressing signal transfer function peaking in a feedforward delta sigma converter 有权抑制前馈ΔΣ转换器中的信号传递函数峰值公开(公告)号：US09564916B2
公开(公告)日：2017-02-07
申请号：US15067847
申请日：2016-03-11
Applicant: ANALOG DEVICES, INC.
Inventor： Abhishek Bandyopadhyay
IPC: H03M3/00
Abstract: A modified topology for a CTDSM (referred herein as “SCFF”) can effectively deal with signal transfer function (STF) peaking, an inherent property of continuous time feedforward delta sigma converters. The SCFF approach involves providing an additional digital-to-analog (DAC) feedback path to the input of the second integrator (incurring an additional DAC in the circuitry, converting the output of the quantizer into an analog signal and feeding the analog signal to the input of the second integrator). Furthermore, the SCFF approach involves providing two feed-ins: a first feed-in to the input of the second integrator and a second feed-in to the input of the third integrator. The first feed-in can be negative. Advantageously, the modified continuous time delta sigma modulator implementing this approach alleviates some of the peaking issues in the signal transfer function while still enjoy low power consumption.
Abstract translation: 用于CTDSM（本文称为“SCFF”）的修改拓扑可以有效地处理信号传递函数（STF）峰值，这是连续时间前馈Δ-Σ转换器的固有特性。 SCFF方法包括为第二积分器的输入提供额外的数模（DAC）反馈路径（在电路中产生附加的DAC，将量化器的输出转换为模拟信号，并将模拟信号馈送到 第二积分器的输入）。 此外，SCFF方法包括提供两个馈入：第二积分器的输入的第一馈入和第三积分器的输入的第二馈入。 第一个馈入可以是否定的。 有利地，实现该方法的经修改的连续时间ΔΣ调制器减轻了信号传递功能中的一些峰值问题，同时仍享有低功耗。
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