公开(公告)号：US11990911B2

公开(公告)日：2024-05-21

申请号：US17654916

申请日：2022-03-15

申请人： QUALCOMM Incorporated

发明人： Negar Rashidi ,  Nitz Saputra ,  Ashok Swaminathan

IPC分类号： H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/82

CPC分类号： H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H03M1/82

摘要： In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

公开(公告)号：US11742869B2

公开(公告)日：2023-08-29

申请号：US17573212

申请日：2022-01-11

申请人： Mellanox Technologies, Ltd.

发明人： Anthony Eugene Zortea ,  Hananel Faig ,  Boris Sharav ,  Mor Goren ,  Alik Gorshtein ,  Nir Sheffi

IPC分类号： H03M1/06 ,  H03M1/10

CPC分类号： H03M1/0624 ,  H03M1/1023

摘要： A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.

公开(公告)号：US20230188155A1

公开(公告)日：2023-06-15

申请号：US18167380

申请日：2023-02-10

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Artem Vitalyevich CHERENKOV ,  Man ZHAO ,  Mikhail Alexandrovich LINNIK ,  Yijie WANG

IPC分类号： H03M1/66 ,  H03M1/06 ,  H03M1/12 ,  H03M1/08

CPC分类号： H03M1/662 ,  H03M1/0624 ,  H03M1/1215 ,  H03M1/0854

摘要： A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.

公开(公告)号：US11646747B1

公开(公告)日：2023-05-09

申请号：US17580805

申请日：2022-01-21

申请人： Caelus Technologies Limited

发明人： Chi Fung Lok

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/38 ,  H03M1/06

CPC分类号： H03M1/1057 ,  H03M1/1215 ,  H03M1/0624 ,  H03M1/1014 ,  H03M1/1023 ,  H03M1/12 ,  H03M1/38

摘要： An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.

公开(公告)号：US20180323794A1

公开(公告)日：2018-11-08

申请号：US15774455

申请日：2016-11-04

申请人： Teledyne e2v Semiconductors SAS

发明人： Etienne BOUIN ,  Rémi LAUBE ,  Jérôme LIGOZAT ,  Marc STACKLER

IPC分类号： H03M1/06

CPC分类号： H03M1/0624 ,  H03K5/1534 ,  H03K2005/00267 ,  H03M1/1215

摘要： In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

公开(公告)号：US20180234103A1

公开(公告)日：2018-08-16

申请号：US15895453

申请日：2018-02-13

申请人： Infineon Technologies AG

发明人： Jens Barrenscheen ,  Peter Bogner ,  Juergen Schaefer

IPC分类号： H03M1/12

CPC分类号： H03M1/1245 ,  H02M3/33546 ,  H02P27/06 ,  H03M1/0624 ,  H03M1/122

摘要： An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

公开(公告)号：US20180167080A1

公开(公告)日：2018-06-14

申请号：US15823355

申请日：2017-11-27

申请人： Rambus Inc.

发明人： Kenneth C. Dyer

IPC分类号： H03M1/12 ,  H03M1/06 ,  H03M1/08

CPC分类号： H03M1/1255 ,  H03M1/0624 ,  H03M1/0673 ,  H03M1/0836 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1215

摘要： An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M−1 sampling phases of the M sampling phases. The phase control circuit comprises M−1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M−1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.

公开(公告)号：US09980683B2

公开(公告)日：2018-05-29

申请号：US15504259

申请日：2015-08-05

申请人： Hitachi, Ltd.

发明人： Masafumi Onouchi

IPC分类号： H03M1/06 ,  A61B6/03 ,  H03M1/12

CPC分类号： A61B6/035 ,  A61B6/03 ,  H03M1/0624 ,  H03M1/1245 ,  H03M1/1265

摘要： In order to provide a highly precise analog/digital conversion system in which an output error of an AD converter is small, sampling is performed at a certain sampling period S from the start time of a measurement period TL to the (N−1)-th sampling when the measurement period TL does not correspond to the sampling period S multiplied by the number of samplings N, the N-th sampling is performed at a timing when a time interval between the (N−1)-th sampling and the N-th sampling is equal to the sampling period S multiplied by a predetermined coefficient k, and the k value is set to a non-integer optimum value evaluated in advance in accordance with the N value in order to minimize an error of the detection value of the AD converter.

公开(公告)号：US09800228B2

公开(公告)日：2017-10-24

申请号：US14859899

申请日：2015-09-21

申请人： Rohde & Schwarz GmbH & Co. KG

发明人： Ols Hidri

IPC分类号： H03H11/26 ,  G01R13/02 ,  H03K5/159 ,  H03M1/12

CPC分类号： H03H11/265 ,  G01R13/0272 ,  H03K5/159 ,  H03M1/0624 ,  H03M1/1215 ,  H03M1/124

摘要： A delay line device is provided for a high frequency sampler for high frequency signal transmission, or for an oscilloscope for measuring high frequency signals. The delay line device includes two distributed tapped transmission delay lines. Each of the delay lines includes two terminals. An analog input signal is applied to a first terminal of the first delay line, and a clock signal is applied to a first terminal of the second delay line. The delay lines are configured such that the analog input signal propagates through the first delay line in an opposite direction as compared to the propagation of the clock signal through the second delay line.

公开(公告)号：US20170257109A1

公开(公告)日：2017-09-07

申请号：US15427014

申请日：2017-02-07

申请人： Silicon Laboratories Inc.

发明人： Wajid Hassan Minhass ,  Oeivind A. G. Loe

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/12 ,  H03M1/002 ,  H03M1/0624

摘要： An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.