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公开(公告)号：US20240340019A1
公开(公告)日：2024-10-10
申请号：US18745800
申请日：2024-06-17
摘要： A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
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公开(公告)号：US12113544B2
公开(公告)日：2024-10-08
申请号：US17864464
申请日：2022-07-14
发明人： Sheng-Yen Shih , Shih-Hsiung Huang , Wei-Cian Hong
CPC分类号： H03M1/38 , H03M1/1245 , H03M3/04
摘要： A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.
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公开(公告)号：US20240333297A1
公开(公告)日：2024-10-03
申请号：US18612301
申请日：2024-03-21
申请人： ROHM CO., LTD.
发明人： Naohiro NOMURA
IPC分类号： H03M1/38
CPC分类号： H03M1/38
摘要： A successive approximation type A/D converter includes: a capacitive D/A converter, and a buffer circuit configured to supply a reference voltage to the capacitive D/A converter, wherein the buffer circuit includes: a reference voltage source configured to generate a constant voltage, a first stage amplifier configured to amplify the constant voltage, an output buffer with a gain of 1 configured to receive a voltage according to an output voltage of the first stage amplifier, and a filter that is interposed between the first stage amplifier and the output buffer and acts on a signal directed from the output buffer to the first stage amplifier, and wherein a tail current of a differential amplifier of the output buffer is larger than a tail current of a differential amplifier of the first stage amplifier.
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公开(公告)号：US12047087B2
公开(公告)日：2024-07-23
申请号：US17771268
申请日：2019-10-31
摘要： An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
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公开(公告)号：US20240192575A1
公开(公告)日：2024-06-13
申请号：US18532400
申请日：2023-12-07
申请人： LX SEMICON CO., LTD.
发明人： Hyung Seup KIM , Kyu Ho KIM , Dong Hwan YOON , Jin Kook YUN , Dong Gil JEONG
CPC分类号： G03B5/00 , H03K5/003 , H03M1/38 , G03B2205/0007
摘要： An analog front-end circuit includes a hall bias correction loop circuit configured to correct a sensing voltage of a hall sensor by adjusting a hall bias current flowing in the hall sensor while tracking a change in the sensing voltage of the hall sensor based on a temperature change, an offset correction loop circuit configured to correct an offset correction voltage while tracking an offset change of the hall sensor and an offset change of an amplifier circuit based on the temperature change, the amplifier circuit configured to amplify and output the sensing voltage of the hall sensor, corrected through at least one of the hall bias correction loop circuit and the offset correction loop circuit, and an analog-digital converter configured to convert an output voltage of the amplifier circuit into sensing data and output the sensing data.
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公开(公告)号：US20240187014A1
公开(公告)日：2024-06-06
申请号：US18285217
申请日：2022-03-31
发明人： Henrik FON
摘要： A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.
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公开(公告)号：US20240178857A1
公开(公告)日：2024-05-30
申请号：US18335572
申请日：2023-06-15
发明人： Jihwan HYUN , Chulwoo KIM , Sooho PARK , Junghwan CHOI
CPC分类号： H03M1/38 , H03M1/1245
摘要： In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.
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8.发明公开公开(公告)号：US20240171180A1
公开(公告)日：2024-05-23
申请号：US18429890
申请日：2024-02-01
发明人： GUO-HAU LEE , HUAI-TE WANG , CHENG-LIANG HUNG
CPC分类号： H03L7/0807 , H03K3/037 , H03L7/0893 , H03L7/091 , H03L7/0992 , H03L7/0995 , H03L7/189 , H03M1/38
摘要： A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
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公开(公告)号：US20240137033A1
公开(公告)日：2024-04-25
申请号：US18047896
申请日：2022-10-18
发明人： Marc Kanzian , Alan Paussa , Francesco Conzatti , Joseph Semmler
CPC分类号： H03M1/1009 , H03M1/38
摘要： In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.
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公开(公告)号：US20240120932A1
公开(公告)日：2024-04-11
申请号：US18527355
申请日：2023-12-03
发明人： Yabo NI , Yong ZHANG , Xiaofeng SHEN , Ting LI , Lu LIU , Can ZHU , Jiahao PENG , Liang LI , Dongbing FU , Jianan WANG
CPC分类号： H03M1/164 , H03M1/1038 , H03M1/38
摘要： Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.
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