SYSTEMS, METHODS, AND DEVICES FOR EFFICIENT EXECUTION OF ARTIFICIAL NEURAL NETWORKS

    公开(公告)号:US20230128057A1

    公开(公告)日:2023-04-27

    申请号:US17965166

    申请日:2022-10-13

    Abstract: A system for executing an artificial neural network having a plurality of interconnected nodes, the system includes a memory storing weight values of the neural network. The memory can be configured to a store node value and a mask bit value for each of the plurality of nodes of the neural network. Further the system can include multiply and accumulate (MAC) units to perform operations for determining node values. The system includes a control unit circuitry that, during execution of the neural network, dynamically controls operations of the MAC units to cause a reduction in a number of calculations to be performed by the MAC units. The control unit circuitry causes the MAC units to perform operations involving a subset of the plurality of nodes to avoid performing operations involving nodes of the plurality nodes that are outside of the subset.

    Non-linear inter-ADC calibration by time equidistant triggering

    公开(公告)号:US11621717B1

    公开(公告)日:2023-04-04

    申请号:US17519759

    申请日:2021-11-05

    Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

    Method for driving a load
    6.
    发明授权
    Method for driving a load 有权
    驾驶负载的方法

    公开(公告)号:US09374081B2

    公开(公告)日:2016-06-21

    申请号:US13745516

    申请日:2013-01-18

    CPC classification number: H03K17/284 H03K17/166

    Abstract: An electronic switch includes a load path connected in series with the load and a drive terminal for receiving a drive signal. The electronic switch is operable to switch between a first operation state and a second operation state dependent on the drive signal. In a first switching cycle, the electronic switch is switched from the first operation state to the second operation state and a voltage across the load is evaluated during the first switching cycle in order to obtain a measured switching profile. The measured switching profile is compared with a reference profile. A drive profile dependent on the comparison is provided. The drive profile is used to drive the electronic switch in a second switching cycle after the first switching cycle. At least two drive parameters are used at different times in the at least one second switching cycle to drive the electronic switch.

    Abstract translation: 电子开关包括与负载串联连接的负载路径和用于接收驱动信号的驱动端子。 电子开关可操作以取决于驱动信号在第一操作状态和第二操作状态之间切换。 在第一开关周期中,电子开关从第一操作状态切换到第二操作状态,并且在第一开关周期期间评估负载两端的电压,以获得测量的开关曲线。 将测量的切换轮廓与参考轮廓进行比较。 提供了依赖于比较的驱动器配置文件。 驱动器配置文件用于在第一个开关周期之后的第二个开关周期中驱动电子开关。 在至少一个第二切换周期中,在不同时间使用至少两个驱动参数来驱动电子开关。

    IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS

    公开(公告)号:US20220179012A1

    公开(公告)日:2022-06-09

    申请号:US17114915

    申请日:2020-12-08

    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

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