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公开(公告)号：US12028069B2
公开(公告)日：2024-07-02
申请号：US17742112
申请日：2022-05-11
申请人： Kratos SRE, Inc.
发明人： Seth D. Cohen
摘要： Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.
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公开(公告)号：US11984908B2
公开(公告)日：2024-05-14
申请号：US17298449
申请日：2019-11-27
申请人： Microvision, Inc.
发明人： Ralf Beuschel
IPC分类号： H03M1/50 , G01S7/484 , G01S7/4865 , H03M1/56 , G01S17/931
CPC分类号： H03M1/56 , G01S7/484 , G01S7/4866 , G01S17/931
摘要： Described herein are analog-to-digital converters (ADCs) that utilize time-to-digital converters (TDCs) and a histogram block to generate time-correlated histograms from analog signals. In some implementations, the time-to-digital converters determine time intervals for which the analog signal above or below a ramp signal, and the histogram block generates the time-correlated histograms of values using the determined time intervals. Furthermore, in some implementations, the analog-to-digital converters receive the analog signals from photodiodes, such as photo diodes used in Light Detection and Ranging (LIDAR) devices. In some such applications, the use of time intervals to generate time-correlated histograms may be used to reduce the effects of time jitter.
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公开(公告)号：US11936398B2
公开(公告)日：2024-03-19
申请号：US17041630
申请日：2019-03-26
CPC分类号： H03M1/164 , G01S7/52023 , G04F10/005 , H03M1/50 , H04B11/00 , H03M3/30
摘要： The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.
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4.发明公开公开(公告)号：US20230308112A1
公开(公告)日：2023-09-28
申请号：US17704511
申请日：2022-03-25
发明人： Avri HARUSH
CPC分类号： H03M3/424 , H03M1/502 , G04F10/005 , H03L7/0991
摘要： A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.
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公开(公告)号：US11742872B2
公开(公告)日：2023-08-29
申请号：US17728985
申请日：2022-04-26
发明人： Eizo Ichihara , Shintaro Kawazoe
CPC分类号： H03M1/1245 , H03M1/0854 , H03M1/361 , H03M1/50 , H03M3/39
摘要： Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.
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公开(公告)号：US20230170800A1
公开(公告)日：2023-06-01
申请号：US17994134
申请日：2022-11-25
发明人： Huidong Gwon , Byongdeok Choi , Taehwang Kong , Junhyeok Yang , Junhwan Jang
CPC分类号： H02M3/157 , H03M1/44 , H03M1/502 , H03M1/0607
摘要： An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.
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公开(公告)号：US20230087101A1
公开(公告)日：2023-03-23
申请号：US17886033
申请日：2022-08-11
发明人： Yoichi IIZUKA , Fukashi MORISHITA
摘要： An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
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公开(公告)号：US11500336B1
公开(公告)日：2022-11-15
申请号：US17317628
申请日：2021-05-11
摘要： An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.
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公开(公告)号：US11475288B2
公开(公告)日：2022-10-18
申请号：US16674488
申请日：2019-11-05
摘要： Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.
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10.发明申请公开(公告)号：US20220262426A1
公开(公告)日：2022-08-18
申请号：US17351280
申请日：2021-06-18
发明人： Lih-Yih Chiou , Yu-Wei Lin , Wei-Shuo Ling
IPC分类号： G11C11/4096 , G11C11/4094 , G11C11/408 , G11C11/4074 , H03M1/50 , H03M1/60
摘要： A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.
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