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1.发明申请公开(公告)号：US20190123757A1
公开(公告)日：2019-04-25
申请号：US16158948
申请日：2018-10-12
发明人： Chih-Lung CHEN , Shih-Hsiung HUANG , Chien-Ming WU , Jie-Fan LAI
CPC分类号： H03M1/442 , H03M1/1245 , H03M1/164
摘要： A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.
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公开(公告)号：US20190007071A1
公开(公告)日：2019-01-03
申请号：US16125826
申请日：2018-09-10
CPC分类号： H03M13/39 , H03M1/0641 , H03M1/1014 , H03M1/1245 , H03M1/164 , H03M13/1145
摘要： A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.
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3.发明申请公开(公告)号：US20180323796A1
公开(公告)日：2018-11-08
申请号：US16031753
申请日：2018-07-10
CPC分类号： H03M1/466 , H03M1/0863 , H03M1/1009 , H03M1/124 , H03M1/1245 , H03M1/164 , H03M1/38 , H03M1/44
摘要： An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
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公开(公告)号：US20170302289A1
公开(公告)日：2017-10-19
申请号：US15339200
申请日：2016-10-31
发明人： Martin KINYUA
CPC分类号： H03M1/124 , G04F10/005 , H03M1/1023 , H03M1/164 , H03M1/502 , H04N5/378
摘要： An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.
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公开(公告)号：US20170302287A1
公开(公告)日：2017-10-19
申请号：US15485552
申请日：2017-04-12
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
摘要： The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
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公开(公告)号：US20170187387A1
公开(公告)日：2017-06-29
申请号：US15455971
申请日：2017-03-10
发明人： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
摘要： System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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公开(公告)号：US20160380644A1
公开(公告)日：2016-12-29
申请号：US15258237
申请日：2016-09-07
发明人： Roswald Francis
CPC分类号： H03M1/001 , H03F3/45 , H03F3/45183 , H03F3/45188 , H03F3/45237 , H03F3/45479 , H03F3/45636 , H03F3/505 , H03F2203/45022 , H03F2203/45188 , H03F2203/45404 , H03F2203/45406 , H03F2203/45421 , H03F2203/45461 , H03F2203/45514 , H03F2203/45634 , H03M1/1245 , H03M1/164 , H03M1/44
摘要： Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed.
摘要翻译： 公开了伸缩放大器电路。 在一个实施例中，伸缩放大器包括用于接收差分输入信号的输入级，用于在第一输出晶体管和第二输出晶体管的漏极处输出差分输出信号的输出级，耦合到第一输入端的源极的尾电流晶体管 晶体管和第二输入晶体管，耦合到差分输出信号并输出共模输出信号的共模反馈电路以及耦合在共模输出信号和尾电流晶体管的栅极之间的电路元件。 在一个实施例中，电路元件是电阻器。 在另一个实施例中，电路元件是源极跟随器晶体管。 在另外的实施例中，放大器的共模反馈开环增益的相位裕度由电阻器的值确定。 公开了另外的实施例。
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8.发明授权Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters 有权开关电流管线模数转换器中残余放大器的共模采样机制公开(公告)号：US09503119B2
公开(公告)日：2016-11-22
申请号：US14714602
申请日：2015-05-18
发明人： Jesse Coulon , Manar El-Chammas , Xiaopeng Li , Shigenobu Kimura
CPC分类号： H03M1/72 , H03F3/45094 , H03F3/45565 , H03F2203/45396 , H03F2203/45418 , H03F2203/45424 , H03F2203/45431 , H03M1/0607 , H03M1/164 , H03M1/44
摘要： A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.
摘要翻译： 开关电流管线模数转换器（ADC）集成电路。 集成电路包括跟踪和保持电路（T / H）和残留放大器。 T / H被配置为基于模拟输入产生T / H的差分输出。 残余放大器耦合到T / H，其被配置为在周期性脉冲间隔期间捕获T / H的差分输出的共模信号的样本，其中脉冲间隔小于所述T / H的持续时间的一半 脉冲的周期，被配置为基于部分地基于T / H的差分输出的共模信号的采样来生成校正的输入共模反馈信号，并且被配置为基于所述T / H的差分输出产生差分输出 T / H的差分输出和基于校正的输入共模反馈信号。
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公开(公告)号：US20160274546A1
公开(公告)日：2016-09-22
申请号：US15065395
申请日：2016-03-09
IPC分类号： G04F10/00
CPC分类号： G04F10/005 , H03M1/069 , H03M1/145 , H03M1/164 , H03M1/50
摘要： According to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.
摘要翻译： 根据一个实施例，第一AD转换器将第一电压转换成第一数字信号。 电压/时间转换电路获取对应于第一电压和将第一数字信号转换为模拟信号的结果之间的差值的残差，并将残差转换为根据第一电容器中的电压的时间信号。 时间/电压转换电路根据第二电容器中的电压将时间信号转换成电压信号。 第二AD转换器将电压信号转换成第二数字信号。 数字处理电路输出第三数字信号，以基于第二数字信号调整第一或第二电流源的电流值。
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10.发明授权Switched capacitor circuit and compensation method thereof, and analog to digital converter 有权开关电容电路及其补偿方法，以及模数转换器公开(公告)号：US09413377B1
公开(公告)日：2016-08-09
申请号：US14968924
申请日：2015-12-15
发明人： Soon-Jyh Chang , Tz-Jing Shau , Chung-Ming Huang
CPC分类号： H03H19/006 , H03H19/004 , H03M1/164
摘要： A switched capacitor circuit with feedback compensation is provided. First terminals of a feedback capacitor and at least one capacitor are coupled to a first input terminal of a differential amplifier. Second terminals of the feedback capacitor and the capacitor are coupled to an input terminal during a first period. A feedback compensation circuit amplifies a first voltage on the first input terminal of the differential amplifier by a gain greater than one to generate a second voltage. The second terminal of the feedback capacitor is coupled to the output terminal of the differential amplifier, and the feedback compensation circuit applies the second voltage to the second terminal of the capacitor during a second period.
摘要翻译： 提供具有反馈补偿的开关电容电路。 反馈电容器和至少一个电容器的第一端子耦合到差分放大器的第一输入端子。 反馈电容器和电容器的第二端子在第一时段期间耦合到输入端子。 反馈补偿电路通过大于1的增益来放大差分放大器的第一输入端上的第一电压以产生第二电压。 反馈电容器的第二端子耦合到差分放大器的输出端子，并且反馈补偿电路在第二周期期间将第二电压施加到电容器的第二端子。
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