知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.018 秒)

    Multi-Bit Voltage-to-Delay Conversion in Data Converter Circuitry
    2.
    发明公开
    Multi-Bit Voltage-to-Delay Conversion in Data Converter Circuitry 审中-公开

    公开(公告)号：US20240072820A1

    公开(公告)日：2024-02-29

    申请号：US17898844

    申请日：2022-08-30

    申请人： Texas Instruments Incorporated

    发明人： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

    IPC分类号： H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

    CPC分类号： H03M1/1245 ,  H03M1/44 ,  H03M1/50 ,  H03M1/785

    摘要： An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

    Analog-to-digital convertor pseudo periodic IL estimation
    3.
    发明授权
    Analog-to-digital convertor pseudo periodic IL estimation 有权

    公开(公告)号：US11569827B1

    公开(公告)日：2023-01-31

    申请号：US17390362

    申请日：2021-07-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sthanunathan Ramakrishnan ,  Nithin Gopinath ,  Sai Aditya Nurani ,  Joseph Palackal Mathew ,  Nagalinga Swamy Basayya Aremallapur

    IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/08 ,  H03M1/10

    摘要： Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

    Switched Capacitor Slew Boost Technique
    5.
    发明申请
    Switched Capacitor Slew Boost Technique 有权

    公开(公告)号：US20210091778A1

    公开(公告)日：2021-03-25

    申请号：US16575874

    申请日：2019-09-19

    申请人： Texas Instruments Incorporated

    发明人： Neeraj Shrivastava ,  Sai Aditya Nurani

    IPC分类号： H03M1/12 ,  G06F1/26

    摘要： In described examples, a switched capacitor circuit includes an amplifier that generates a first output signal in response to a first sampled input signal. A second sampling circuit is coupled to the amplifier and generates an output signal in response to the first output signal. A first current boost circuit is coupled to the amplifier and the second sampling circuit and provides current to the second sampling circuit when the first output signal is below a first threshold. A second current boost circuit is coupled to the amplifier and the second sampling circuit and receives current from the second sampling circuit when the first output signal is above a second threshold.