- Patent Title: Multi-bit voltage-to-delay conversion in data converter circuitry
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Application No.: US17898844Application Date: 2022-08-30
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Publication No.: US12191877B2Publication Date: 2025-01-07
- Inventor: Sai Aditya Nurani , Rishi Soundararajan , Nithin Gopinath , Visvesvaraya Pentakota , Shagun Dusad
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H03M1/44 ; H03M1/50 ; H03M1/78

Abstract:
An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
Public/Granted literature
- US20240072820A1 Multi-Bit Voltage-to-Delay Conversion in Data Converter Circuitry Public/Granted day:2024-02-29
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