公开(公告)号：US11569827B1

公开(公告)日：2023-01-31

申请号：US17390362

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sthanunathan Ramakrishnan ,  Nithin Gopinath ,  Sai Aditya Nurani ,  Joseph Palackal Mathew ,  Nagalinga Swamy Basayya Aremallapur

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08 ,  H03M1/10

Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

公开(公告)号：US12224761B2

公开(公告)日：2025-02-11

申请号：US17729374

申请日：2022-04-26

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

IPC: H03M1/20 ,  H03M1/06

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

公开(公告)号：US20220247420A1

公开(公告)日：2022-08-04

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11955984B2

公开(公告)日：2024-04-09

申请号：US17828967

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Viswanathan Nagarajan ,  Aniket Datta ,  Nithin Gopinath

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US20230344436A1

公开(公告)日：2023-10-26

申请号：US17729374

申请日：2022-04-26

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

IPC: H03M1/06

CPC classification number: H03M1/0641 ,  H03M1/0626

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

公开(公告)号：US12191877B2

公开(公告)日：2025-01-07

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US20250004049A1

公开(公告)日：2025-01-02

申请号：US18217292

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Sai Aditya Nurani ,  Viswanathan Nagarajan ,  Himanshu Varshney ,  Mishab I ,  Mujammil Patel

IPC: G01R31/317

Abstract: An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

公开(公告)号：US12074607B2

公开(公告)日：2024-08-27

申请号：US17825864

申请日：2022-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Nithin Gopinath ,  Viswanathan Nagarajan ,  Neeraj Shrivastava ,  Visvesvaraya A. Pentakota ,  Harshit Moondra ,  Abhinav Chandra

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US20240072820A1

公开(公告)日：2024-02-29

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

CPC classification number: H03M1/1245 ,  H03M1/44 ,  H03M1/50 ,  H03M1/785

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.