公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11831283B2

公开(公告)日：2023-11-28

申请号：US17210251

申请日：2021-03-23

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

IPC: H03F1/56 ,  H03G1/00 ,  G01S7/52 ,  H03F3/45 ,  H03G3/30

CPC classification number: H03F1/56 ,  H03F3/45475 ,  G01S7/52033 ,  H03F2203/45134 ,  H03F2203/45151 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03G1/0035 ,  H03G3/301 ,  H03G3/3005

Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

公开(公告)号：US11139799B2

公开(公告)日：2021-10-05

申请号：US16943561

申请日：2020-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan Miglani ,  Shagun Dusad

IPC: H03H11/12 ,  G06F1/10 ,  H03K19/20

Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.

公开(公告)号：US11031947B2

公开(公告)日：2021-06-08

申请号：US16860334

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Chirag Chandrahas Shetty ,  Visvesvaraya Appala Pentakota

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

公开(公告)号：US10985769B2

公开(公告)日：2021-04-20

申请号：US16828149

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Reddy Patukuri ,  Jagannathan Venkataraman ,  Shagun Dusad

IPC: H03M1/08 ,  H04B1/40 ,  H03M1/10

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

公开(公告)号：US10790841B2

公开(公告)日：2020-09-29

申请号：US16221323

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Kumar Reddy Naru ,  Anand Jerry George ,  Shagun Dusad ,  Visvesvaraya Appala Pentakota

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/18

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

公开(公告)号：US10523231B1

公开(公告)日：2019-12-31

申请号：US16233642

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya KrishnaSwamy Nurani ,  Shagun Dusad ,  Visvesvaraya Appala Pentakota

IPC: H03M1/38 ,  H03M1/16 ,  H03M1/12 ,  H03M1/46

Abstract: A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.

公开(公告)号：US20250030390A1

公开(公告)日：2025-01-23

申请号：US18678818

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Vysakh K ,  Shagun Dusad ,  Rajendrakumar Joish

IPC: H03F3/45

Abstract: A cascode amplifier including an amplifier transistor, a cascode transistor, and a current injection circuit. The amplifier transistor has a first current terminal receiving a first power supply voltage, a second current terminal, and a control terminal receiving an input signal. The cascode transistor has a first current terminal coupled to the second current terminal of the amplifier transistor, a second current terminal coupled to an output terminal; and a control terminal receiving a bias voltage. The current injection circuit has an input receiving the input signal, and first and second outputs coupled to the first and second current terminals of the cascode transistor, respectively. The current injection circuit is configured to present out-of-phase currents to the cascode transistor responsive to the input signal.

公开(公告)号：US12191877B2

公开(公告)日：2025-01-07

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US20240072820A1

公开(公告)日：2024-02-29

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

CPC classification number: H03M1/1245 ,  H03M1/44 ,  H03M1/50 ,  H03M1/785

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.