公开(公告)号：US12101096B2

公开(公告)日：2024-09-24

申请号：US17182339

申请日：2021-02-23

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Eeshan Miglani ,  Visvesvaraya Appala Pentakota ,  Kartik Goel ,  Jagannathan Venkataraman ,  Sai Aditya Krishnaswamy Nurani

IPC: H03M1/10 ,  H03K5/24 ,  H03M1/00 ,  H03M1/06

CPC classification number: H03M1/0612 ,  H03K5/2481 ,  H03M1/002 ,  H03M1/1057

Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.

公开(公告)号：US11956340B1

公开(公告)日：2024-04-09

申请号：US17956487

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

公开(公告)号：US20240113851A1

公开(公告)日：2024-04-04

申请号：US17956487

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

公开(公告)号：US11722142B1

公开(公告)日：2023-08-08

申请号：US17849594

申请日：2022-06-25

Applicant: Texas Instruments Incorporated

Inventor： Jagannathan Venkataraman ,  Ani Xavier ,  Shyam Subramanian

IPC: H03L7/099

CPC classification number: H03L7/0992

Abstract: In described examples, a charge pump includes an output, first and second transistors, a control circuit, a multiplexer, and a calibration circuit. The first transistor's drain is coupled to the output. The second transistor's drain is part of a current path separate from a current path that includes the first transistor's drain. The control circuit generates a control signal in response to voltages at the gates of the first and second transistors. First and second inputs of the multiplexer are respectively coupled to sources of the first and second transistors. A control input of the multiplexer is coupled to receive the control signal. A first input of the calibration circuit is coupled to an output of the multiplexer. A second input of the calibration circuit receives a reference voltage. First and second outputs of the calibration circuit are respectively coupled to body terminals of the first and second transistors.

公开(公告)号：US20200177288A1

公开(公告)日：2020-06-04

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04L27/36 ,  H04B1/04

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

公开(公告)号：US20200162097A1

公开(公告)日：2020-05-21

申请号：US16748849

申请日：2020-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam ,  Raja Reddy Patukuri ,  Sandeep Kesrimal Oswal

IPC: H03M3/00

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

公开(公告)号：US10362994B2

公开(公告)日：2019-07-30

申请号：US15298764

申请日：2016-10-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hussam Ahmed ,  Jagannathan Venkataraman ,  Sandeep Kesrimal Oswal ,  Antoine Lourdes Praveen Aroul ,  Hari Babu Tippana ,  Anand Hariraj Udupa

IPC: A61B5/1455 ,  A61B5/00 ,  A61B5/0205 ,  A61B5/024

Abstract: A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.

公开(公告)号：US10145736B2

公开(公告)日：2018-12-04

申请号：US15491729

申请日：2017-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hussam Ahmed ,  Jagannathan Venkataraman ,  Sandeep Kesrimal Oswal ,  Hari Babu Tippana ,  Anand Hariraj Udupa

IPC: G01J1/44 ,  H01L31/101 ,  H01L31/107

Abstract: At least some embodiments are directed to a light detection system comprising a photodiode, a transimpedance amplifier (TIA) having a differential output and a differential input coupled across the photodiode, a first bias current source coupled to an anode of the photodiode, and a second bias current source coupled to a cathode of the photodiode. The system also comprises a dynamic control logic coupled to the first and second bias current sources and configured to vary bias currents provided by the first and second bias current sources based on the differential output such that the photodiode is reverse-biased.

公开(公告)号：US20240259175A1

公开(公告)日：2024-08-01

申请号：US18629247

申请日：2024-04-08

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

公开(公告)号：US20240030926A1

公开(公告)日：2024-01-25

申请号：US17873129

申请日：2022-07-25

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman

IPC: H03L7/085 ,  H03L7/083 ,  H03L7/107 ,  H03L7/08

CPC classification number: H03L7/085 ,  H03L7/083 ,  H03L7/1072 ,  H03L7/0807

Abstract: In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.