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公开(公告)号：US11316505B2
公开(公告)日：2022-04-26
申请号：US17181073
申请日：2021-02-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.
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公开(公告)号：US10484001B1
公开(公告)日：2019-11-19
申请号：US16221464
申请日：2018-12-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota , Anand Jerry George
Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.
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公开(公告)号：US10367511B2
公开(公告)日：2019-07-30
申请号：US16036221
申请日：2018-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun Dusad , Visvesvaraya Pentakota , Mark Baxter Weaver , William Bright , Jiankun Hu
Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
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公开(公告)号：US10185339B2
公开(公告)日：2019-01-22
申请号：US14446815
申请日：2014-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shuaeb Fazeel , Eeshan Miglani , Visvesvaraya Pentakota , Shagun Dusad
Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.
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公开(公告)号：US10050632B2
公开(公告)日：2018-08-14
申请号：US15395489
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun Dusad , Visvesvaraya Pentakota , Mark Baxter Weaver , William Bright , Jiankun Hu
Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
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Patent Agency Ranking
公开(公告)号：US10038453B1
公开(公告)日：2018-07-31
申请号：US15792924
申请日：2017-10-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand Jerry George , Rishi Soundararajan , Visvesvaraya Pentakota
CPC classification number: H03M1/1061 , H03M1/0604 , H03M1/468 , H03M1/68 , H03M1/802 , H03M1/804
Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.
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公开(公告)号：US11595053B2
公开(公告)日：2023-02-28
申请号：US17366506
申请日：2021-07-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
IPC: H03M1/20
Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.
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公开(公告)号：US10673452B1
公开(公告)日：2020-06-02
申请号：US16217643
申请日：2018-12-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
IPC: H03M1/20
Abstract: An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.
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公开(公告)号：US10476542B1
公开(公告)日：2019-11-12
申请号：US16274621
申请日：2019-02-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Neeraj Shrivastava , Rajendrakumar Joish , Shagun Dusad , Visvesvaraya Pentakota
IPC: H04B1/04 , H04B1/18 , H03K17/94 , H03K19/173
Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.
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公开(公告)号：US10341082B1
公开(公告)日：2019-07-02
申请号：US15906000
申请日：2018-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan , Shagun Dusad , Visvesvaraya Pentakota , Srinivas Kumar Reddy Naru , Sarma Sundareswara Gunturi , Nagalinga Swamy Basayya Aremallapur
Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
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