公开(公告)号：US20250062683A1

公开(公告)日：2025-02-20

申请号：US18643893

申请日：2024-04-23

Applicant: FARADAY SEMI, INC.

Inventor： Parviz Parto

IPC: H02M3/00 ,  G05F1/46 ,  G06F1/26 ,  H01L29/772 ,  H02M3/156 ,  H02M3/158 ,  H02M3/335 ,  H02M7/00

Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.

公开(公告)号：US12228958B2

公开(公告)日：2025-02-18

申请号：US18359931

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Amit Kundu ,  Jaw-Juinn Horng

IPC: G05F3/26 ,  G05F1/46 ,  G05F1/567

Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

公开(公告)号：US20250044819A1

公开(公告)日：2025-02-06

申请号：US18919594

申请日：2024-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Szu-Chun Tsao ,  Jaw-Juinn Horng ,  Bindu Madhavi Kasina ,  Yi-Wen Chen

IPC: G05F1/46 ,  G05F3/26 ,  G05F3/30

Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.

公开(公告)号：US12204354B2

公开(公告)日：2025-01-21

申请号：US18305960

申请日：2023-04-24

Applicant: Texas Instruments Incorporated

Inventor： Bradford Hunter

IPC: G05F1/46 ,  G05F1/573 ,  G05F3/26

Abstract: An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.

公开(公告)号：US12188870B2

公开(公告)日：2025-01-07

申请号：US17224925

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: H01L27/146 ,  G01N21/64 ,  G05F1/46

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20250004522A1

公开(公告)日：2025-01-02

申请号：US18342341

申请日：2023-06-27

Applicant: NVIDIA Corp.

Inventor： Jiale Liang ,  Prashant Singh ,  Nishit Harshad Shah ,  Daniel Nguyen ,  Kaushik Krishna Raghuraman ,  Suhas Satheesh ,  Ting Lu ,  Roman Surgutchik ,  Tezaswi Raja

IPC: G06F1/28 ,  G05F1/46 ,  G06F1/24

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

公开(公告)号：US12181902B2

公开(公告)日：2024-12-31

申请号：US17683217

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rinu Mathew ,  Vineet Khurana ,  Anand Kumar G ,  Aniruddha Periyapatna Nagendra ,  Venkatesh Kadlimatti ,  Torjus Lyng Kallerud

IPC: H02M1/00 ,  G01R17/04 ,  G05F1/46 ,  H02M3/156 ,  H02M3/157

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

公开(公告)号：US20240404966A1

公开(公告)日：2024-12-05

申请号：US18801005

申请日：2024-08-12

Applicant: Oracle International Corporation

Inventor： Michael Henry Soltau Dayringer ,  Anatoly Yakovlev ,  Ji Eun Jang ,  Hesam Fathi Moghadam ,  David Hopkins

IPC: H01L23/64 ,  G05F1/46 ,  H01F27/24 ,  H01L23/00 ,  H01L23/522 ,  H02M1/00 ,  H02M1/14 ,  H02M3/158

Abstract: Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.

公开(公告)号：US12160164B2

公开(公告)日：2024-12-03

申请号：US17738907

申请日：2022-05-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yu Tanaka

IPC: G01R33/00 ,  G05F1/46 ,  H02M1/00 ,  H02M1/36 ,  H02M3/156

Abstract: A measurement apparatus includes a linear regulator, a switching regulator, an acquisition unit configured to acquire measurement data by sensing a signal as a measurement target, and a control unit configured to selectively drive the linear regulator or the switching regulator, wherein the control unit is configured to select and drive the linear regulator in a first period in which the measurement data is acquired by the acquisition unit, and select and drive the switching regulator in a second period that is different from the first period.

公开(公告)号：US12153457B2

公开(公告)日：2024-11-26

申请号：US18137387

申请日：2023-04-20

Applicant: XILINX, INC.

Inventor： Lakshmi Venkata Satya Lalitha Indumathi Janaswamy ,  Sree Rama Krishna Chaithnya Saraswatula ,  Santosh Yachareni ,  Anil Kumar Kandala ,  Narendra Kumar Pulipati ,  Shidong Zhou

IPC: G05F1/46 ,  G05F1/56

Abstract: A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.