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    CONDUCTIVE MATERIAL DEPOSITION ON SEMICONDUCTOR WITH PHASE TRANSITION AND OHMIC CONTACT IN SITU
    1.
    发明申请
    CONDUCTIVE MATERIAL DEPOSITION ON SEMICONDUCTOR WITH PHASE TRANSITION AND OHMIC CONTACT IN SITU 有权

    公开(公告)号：US20250038004A1

    公开(公告)日：2025-01-30

    申请号：US18782040

    申请日：2024-07-24

    Applicant: The Hong Kong University of Science and Technology

    Inventor： Sen YANG ,  Zeying CHEN ,  Wing Ki LO ,  Ning WANG

    IPC: H01L21/288 ,  H01L29/16 ,  H01L29/24 ,  H01L29/45 ,  H01L29/772

    Abstract: A method for a photon induced conductive material deposition on a substrate is provided. The method includes steps as follows: preparing a first solution comprising metalate, metal ions, or combinations thereof; preparing a first suspension comprising nanoparticles, a light sensitive reducing agent, an electron providing solvent, or combinations thereof; mixing the first solution and the first suspension to form a first reagent on a first substrate; and emitting a light beam provided by a light source and focusing the same onto the first reagent kept on a first region of the first substrate, so as to form a mechanically rigid conductive deposition in contact with the first substrate in a focus point of the light source, wherein the first substrate has a second region exposed to surrounding gas or an air environment.

    SEMICONDUCTOR PACKAGE WITH DIRECTIONAL LOCKING STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE WITH DIRECTIONAL LOCKING STRUCTURE 有权

    公开(公告)号：US20250006602A1

    公开(公告)日：2025-01-02

    申请号：US18753963

    申请日：2024-06-25

    Applicant: Tesla, Inc.

    Inventor： William Thomas Chi ,  Utkarsh Raheja ,  Sesha Sai Srikant Sarma Gandikota ,  Steven Thomas Embleton

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H01L29/772

    Abstract: The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, molding material, and a conductive structure. The conductive structure is at least partly stacked with the semiconductor die, and the conductive structure includes a plurality of slots positioned around a point of the semiconductor die. The plurality of slots is configured to equalize thermal stresses during the operation of the semiconductor die about the point of the semiconductor die, where the thermal stresses are associated with coefficient of thermal expansion mismatches between the conductive structure and the molding material. In addition, at least a portion of the molding material is in contact with the conductive structure.

    SIC STATIC INDUCTION TRANSISTOR WITH DOUBLE SIDE COOLING AND METHOD OF MANUFACTURE
    4.
    发明申请
    SIC STATIC INDUCTION TRANSISTOR WITH DOUBLE SIDE COOLING AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20240371989A1

    公开(公告)日：2024-11-07

    申请号：US18311159

    申请日：2023-05-02

    Applicant: Analog Power Conversion LLC

    Inventor： Dumitru G. SDRULLA ,  Amaury Gendron-Hansen ,  Wang-Chang A. Gu

    IPC: H01L29/772 ,  H01L23/373 ,  H01L23/528 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

    Abstract: A silicon carbide (SiC) static induction transistor (SIT) includes a source, a gate disposed over the source and receiving a control signal, a drain disposed over the recessed gate and generating an output signal, an epitaxial pattern disposed between the source and the drain and including a protruding portion, and a gate bus electrically coupled to the gate and including carbon. A method of forming an SiC SIT transistor device includes providing a substrate including a source doped with dopants of a first conductivity type, forming an epitaxial pattern including a protruding portion over the source, forming a recessed gate over the source, forming a gate bus over the recessed gate, forming a drain over the gate bus and the epitaxial pattern, and forming a first heatsink over the drain.

    POWER SEMICONDUCTOR DEVICE WITH VOLTAGE CLAMP CIRCUIT
    6.
    发明公开
    POWER SEMICONDUCTOR DEVICE WITH VOLTAGE CLAMP CIRCUIT 审中-公开

    公开(公告)号：US20240178830A1

    公开(公告)日：2024-05-30

    申请号：US18070585

    申请日：2022-11-29

    Applicant: Infineon Technologies Austria AG

    Inventor： Kennith Kin Leong

    IPC: H03K17/08 ,  H01L27/02 ,  H01L29/772 ,  H01L29/866

    CPC classification number: H03K17/08 ,  H01L27/0255 ,  H01L29/772 ,  H01L29/866

    Abstract: A power semiconductor device includes: a main power switch having a drain, source, and gate; and a voltage clamp circuit in parallel with the main power switch and having a clamp voltage less than a breakdown voltage of the main power switch. The voltage clamp circuit includes: a pulldown switch having a normally-on gate electrically connected to the source of the main power switch; a plurality of series-connected diodes electrically connected between the drain of the main power switch and a drain of the pulldown switch; a voltage clamp device electrically connected between a source of the pulldown switch and the source of the main power switch; and a second power switch having a normally-off gate electrically connected to the drain of the pulldown switch, a drain electrically connected to the drain of the main power switch, and a source electrically connected to the source of the pulldown switch.

    STACKED SEMICONDUCTOR CHIP STRUCTURE AND ITS PROCESS
    7.
    发明申请
    STACKED SEMICONDUCTOR CHIP STRUCTURE AND ITS PROCESS 有权

    公开(公告)号：US20220085188A1

    公开(公告)日：2022-03-17

    申请号：US17103876

    申请日：2020-11-24

    Applicant: Bo TU ,  Hsiang-Yi CHENG

    Inventor： Bo TU ,  Hsiang-Yi CHENG

    IPC: H01L29/66 ,  H01L29/772 ,  H01L49/02

    Abstract: The present invention discloses a stacked semiconductor chip structure and its process wherein the stacked semiconductor chip structure comprises a substrate as well as P-type semiconductor layers and N-type semiconductor layers which are stacked one by one on the substrate, wherein the P-type semiconductor layers and the N-type semiconductor layers are arranged alternately, there are at least two P-type semiconductor layers and at least two N-type semiconductor layers. The present invention uses the chemical vapor deposition method to stack and form the P-type semiconductor layers and the N-type semiconductor layers, uses the physical etching and the plasma cleaning to form the conducting layers and thus avoids using the photo masks, the photo resist and the mask aligners for the manufacture of semiconductor chips, reduces the complexity of semiconductor chip processes and increases the yield of semiconductor chip products.

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