公开(公告)号：US12073869B2

公开(公告)日：2024-08-27

申请号：US17734701

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  H03M1/80

CPC classification number: G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  H03M1/802

Abstract: A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.

公开(公告)号：US20240162915A1

公开(公告)日：2024-05-16

申请号：US18418957

申请日：2024-01-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Gavin MCVEIGH

IPC: H03M1/78 ,  G01L1/22 ,  H03M1/06 ,  H03M1/16 ,  H03M1/66 ,  H03M1/80

CPC classification number: H03M1/785 ,  G01L1/2268 ,  H03M1/0607 ,  H03M1/16 ,  H03M1/662 ,  H03M1/802 ,  H03F3/45

Abstract: The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

公开(公告)号：US11750209B2

公开(公告)日：2023-09-05

申请号：US17310860

申请日：2020-02-26

Applicant: Intel Corporation

Inventor： Franz Kuttner

IPC: H03M1/80 ,  H04B1/04 ,  H03K19/20

CPC classification number: H03M1/802 ,  H04B1/04 ,  H03K19/20

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50Ω.

公开(公告)号：US10038453B1

公开(公告)日：2018-07-31

申请号：US15792924

申请日：2017-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Jerry George ,  Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/80 ,  H03M1/68 ,  H03M1/46

CPC classification number: H03M1/1061 ,  H03M1/0604 ,  H03M1/468 ,  H03M1/68 ,  H03M1/802 ,  H03M1/804

Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.

公开(公告)号：US09331086B2

公开(公告)日：2016-05-03

申请号：US13055211

申请日：2009-07-14

Applicant: Wibo D. Van Noort ,  Theodore J. Letavic ,  Francis Zaato

Inventor： Wibo D. Van Noort ,  Theodore J. Letavic ,  Francis Zaato

IPC: G11C29/02 ,  H01L27/115 ,  G11C16/04 ,  G11C27/00 ,  H01L27/102 ,  H01L27/105 ,  H01L29/792 ,  H03K5/13 ,  H03M1/80 ,  H01L21/8249 ,  H03K5/00

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C27/005 ,  G11C2216/10 ,  H01L21/8249 ,  H01L27/1026 ,  H01L27/105 ,  H01L27/11517 ,  H01L29/792 ,  H03K5/133 ,  H03K2005/00019 ,  H03M1/802

Abstract: An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Abstract translation: 提供一种集成电路，其包括至少一个第一组，每组具有至少一个模拟单元; 以及至少一个第二组，每个具有至少一个可电连接的半永久开关单元，所述至少一个可电连接的半永久开关单元耦合到第一组的至少模拟单元，用于修整第一组并具有至少一个多次可编程和非易失性单元 MTP）。 每个多次可编程单元（MTP）包括具有隧道氧化物（TO）的浮动栅极（FG）和耦合到浮动栅极（FG）的第一电容器的至少一个MOS晶体管。 第一电容器的电容基本上大于MOS晶体管的栅极沟道电容。

公开(公告)号：US20160056836A1

公开(公告)日：2016-02-25

申请号：US14779064

申请日：2014-03-19

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Tatsuya CHUBACHI ,  Junya NAKANISHI

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/08 ,  H03M1/80

CPC classification number: H03M3/374 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/662 ,  H03M1/802 ,  H03M1/804 ,  H03M3/32 ,  H03M3/502

Abstract: The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.

Abstract translation: 根据本发明的DA转换器包括：第一和第二模拟段单元，多个采样电容器组的电容器，其根据在采样阶段输入的数字信号的信号电平进行充电; 以及计算单元，其以整数相位输出根据所述第一或第二模拟段单元的采样电容器组的每个电容器的充电电压的模拟信号，其中，当所述第一和第二模拟段单元的一个模拟段单元 处于采样阶段，另一个模拟段单元处于积分阶段。

公开(公告)号：US09178522B2

公开(公告)日：2015-11-03

申请号：US14476638

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Emanuele Bodano ,  Peter Bogner ,  Joachim Pichler ,  Mark Schauer

IPC: H03M7/00 ,  H03M1/00 ,  H03M1/44 ,  H03M1/46 ,  G05F1/575 ,  H03M1/38

CPC classification number: H03M1/002 ,  G05F1/575 ,  H03M1/38 ,  H03M1/44 ,  H03M1/46 ,  H03M1/802

Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.

Abstract translation: 一个电路包含一个逐次逼近寄存器和一个带可调电容器的可调电容器，用于调节可调电容器的电容值。 而且，它包括比较器，其具有耦合到可调电容器的端子的输入端和至少一个输出端，其中比较器的输出中的至少一个耦合到逐次逼近寄存器的输入端。 电路还包括耦合到可调电容器的端子的模拟输入端。 电路可以被设置为第一操作状态和第二操作状态，其中电路的输出由逐次逼近寄存器控制在第一操作状态，并且在逐次逼近寄存器中不被控制在第二操作状态，但是 由比较方。

公开(公告)号：US20140253355A1

公开(公告)日：2014-09-11

申请号：US14202823

申请日：2014-03-10

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix

IPC: H03M1/80 ,  H03M3/00

CPC classification number: H03M1/802 ,  H03M1/0665 ,  H03M3/30 ,  H03M3/424 ,  H03M3/464

Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.

Abstract translation: 一种用于Σ-Δ调制器的电荷转移型数模转换器（DAC）包括一个可操作以产生4n + 1输出电平的电容器开关单元，包括：多个第二开关单元，用于将第 具有正或负参考信号的多个参考电容器对; 其中所述多个参考电容器对中的第二端子分别并联耦合; 其中，对于偶数传输，提供单个切换组合以实现线性，并且其中对于奇数传输，提供不同切换组合的平均值以实现线性度; 其中偶数传输是当DAC的输入是偶数时，并且奇数传输是当DAC的输入是奇数时。

公开(公告)号：US08624635B2

公开(公告)日：2014-01-07

申请号：US13690023

申请日：2012-11-30

Applicant: Egalax—Empia Technology Inc.

Inventor： Chin-Fu Chang ,  Guang-Huei Lin

IPC: G11C27/02

CPC classification number: H03K6/00 ,  G06F3/041 ,  G11C27/026 ,  H03M1/00 ,  H03M1/1205 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/468 ,  H03M1/802 ,  H03M1/804

Abstract: The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuits arranged in an array and a plurality of Stage 2 integration circuits arranged in an array. Each of the Stage 1 integration circuits is configured to concurrently integrate an input signal, and to send out a Stage 1 positive signal and a Stage 1 negative signal that is reverse to the Stage 1 positive signal. Each of the Stage 2 integration circuits is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to the corresponding Stage 1 integration circuit to output a Stage 2 signal.

Abstract translation: 本发明提供了一种用于同时整合多个差分信号的电路。 该电路包括排列成阵列的多个阶段1积分电路和排列成阵列的多个阶段2积分电路。 每个阶段1积分电路被配置为同时整合输入信号，并发出与阶段1正信号相反的阶段1正信号和阶段1负信号。 每个阶段2积分电路被配置为将来自相应级1积分电路发送的级1正信号的差分信号和从相应级1积分电路旁边的另一级1积分电路发送的级1负信号整合到 输出阶段2信号。

公开(公告)号：US20110186919A1

公开(公告)日：2011-08-04

申请号：US13055211

申请日：2009-07-14

Applicant: Wibo D. Van Noort ,  Theodore J. Letavic ,  Francis Zaato

Inventor： Wibo D. Van Noort ,  Theodore J. Letavic ,  Francis Zaato

IPC: H01L27/105 ,  B82Y99/00

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C27/005 ,  G11C2216/10 ,  H01L21/8249 ,  H01L27/1026 ,  H01L27/105 ,  H01L27/11517 ,  H01L29/792 ,  H03K5/133 ,  H03K2005/00019 ,  H03M1/802

Abstract: An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Abstract translation: 提供一种集成电路，其包括至少一个第一组，每组具有至少一个模拟单元; 以及至少一个第二组，每个具有至少一个可电连接的半永久开关单元，所述至少一个可电连接的半永久开关单元耦合到第一组的至少模拟单元，用于修整第一组并具有至少一个多次可编程和非易失性单元 MTP）。 每个多次可编程单元（MTP）包括具有隧道氧化物（TO）的浮动栅极（FG）和耦合到浮动栅极（FG）的第一电容器的至少一个MOS晶体管。 第一电容器的电容基本上大于MOS晶体管的栅极沟道电容。