公开(公告)号：US12118329B2

公开(公告)日：2024-10-15

申请号：US16744824

申请日：2020-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mingu Kang ,  Seyoung Kim ,  Kyu-Hyoun Kim

IPC: G06N3/02 ,  G06F7/523 ,  G06N3/065 ,  G11C27/02

CPC classification number: G06F7/523 ,  G06N3/065 ,  G11C27/026 ,  G06N3/02

Abstract: Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.

公开(公告)号：US20190123756A1

公开(公告)日：2019-04-25

申请号：US16158916

申请日：2018-10-12

Applicant: Realtek Semiconductor Corp.

Inventor： Shih-Hsiung HUANG ,  Chih-Lung CHEN ,  Jie-Fan LAI ,  Chien-Ming WU

IPC: H03M1/44 ,  H03M1/12

CPC classification number: H03M1/442 ,  G11C27/026 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/164

Abstract: A sample-and-hold amplifier includes: a switched capacitor network for conducting a sample -and-hold operation on an input signal to generate a first signal; and an operational amplifier coupled with the switched capacitor network and including multiple candidate capacitors; wherein the operational amplifier is arranged to operably generate an output signal based on the first signal, and to operably switch coupling relationship of the multiple candidate capacitors based on the magnitude of the input signal, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.

公开(公告)号：US20190096501A1

公开(公告)日：2019-03-28

申请号：US16135053

申请日：2018-09-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Mei-Chen Chuang ,  Alan Roth

IPC: G11C27/02 ,  H03M3/00 ,  H03M1/12 ,  H03M1/46

CPC classification number: G11C27/02 ,  G11C27/026 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/46 ,  H03M1/462 ,  H03M3/426

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

公开(公告)号：US20190052251A1

公开(公告)日：2019-02-14

申请号：US16161329

申请日：2018-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： JongPal KIM

IPC: H03K5/003 ,  H03M3/02 ,  A61B5/00 ,  H03F3/45 ,  G11C27/02 ,  A61B5/0428 ,  A61B5/04

CPC classification number: H03K5/003 ,  A61B5/04004 ,  A61B5/0428 ,  A61B5/04288 ,  A61B5/7225 ,  A61B2560/0209 ,  G11C27/024 ,  G11C27/026 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45428 ,  H03F2203/45551 ,  H03M1/124 ,  H03M3/02

Abstract: A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal.

公开(公告)号：US10020069B2

公开(公告)日：2018-07-10

申请号：US14875511

申请日：2015-10-05

Applicant: Forza Silicon Corporation

Inventor： Steven Huang

IPC: H01L27/00 ,  G11C27/02 ,  H04N5/378 ,  H03F3/45

CPC classification number: G11C27/026 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45156 ,  H03F2203/45171 ,  H03F2203/45514 ,  H03F2203/45551 ,  H04N5/378

Abstract: Disclosed herein are novel charge mode readout circuits and associated methods of signal processing. The devices and methods of the invention allow for the improved processing of stored signals by a charge mode readout amplifier, wherein the readout level may be shifted to a desired range and wherein a fully differential output swing may be imparted. The invention advantageously employs a single pair of capacitors to serve the dual roles of modulating amplifier gain and level shifting the output.

公开(公告)号：US09930274B2

公开(公告)日：2018-03-27

申请号：US15198832

申请日：2016-06-30

Applicant: Sony Corporation

Inventor： Noam Eshel ,  Golan Zeituni

IPC: H04N5/363 ,  H03K5/08 ,  H04N5/374 ,  H04N5/378 ,  H04N5/3745 ,  G11C27/02

CPC classification number: H04N5/363 ,  G11C27/026 ,  H03K5/08 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/37457 ,  H04N5/378

Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.

公开(公告)号：US09878627B2

公开(公告)日：2018-01-30

申请号：US14622832

申请日：2015-02-14

Applicant: Hyundai Motor Company

Inventor： Jee Hye Jeong ,  Jae Won Lee ,  Jung Hwan Na

IPC: H02J7/00 ,  B60L11/18 ,  G11C27/02

CPC classification number: B60L11/1816 ,  G11C27/026 ,  H02J7/0021 ,  H02J7/0047 ,  H02J7/007 ,  H02J2007/005 ,  Y02T10/7055

Abstract: An apparatus for detecting a level of a control pilot signal includes: a switch controller configured to output a switch control signal using a control pilot input signal, which was outputted from an electric vehicle supply equipment; and a sample and hold logic unit configured to sample and hold the control pilot input signal, based on the outputted switch control signal, in order to output a control pilot output signal.

公开(公告)号：US20180019717A1

公开(公告)日：2018-01-18

申请号：US15646376

申请日：2017-07-11

Applicant: Seiko Epson Corporation

Inventor： Noriyuki MURASHIMA

IPC: H03F3/387 ,  H03F3/45 ,  G01D5/241 ,  G11C27/02 ,  H03H7/01 ,  H03G3/20

CPC classification number: H03F3/387 ,  G01D5/2417 ,  G01D21/00 ,  G11C27/02 ,  G11C27/026 ,  H03F3/45475 ,  H03F2203/45514 ,  H03G1/0094 ,  H03G3/001 ,  H03G3/20 ,  H03H7/0138 ,  H03H19/004

Abstract: A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.

公开(公告)号：US09847760B1

公开(公告)日：2017-12-19

申请号：US15620171

申请日：2017-06-12

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Rajendrakumar Joish

IPC: H03M1/12 ,  H03F3/00 ,  G11C27/02 ,  H04B1/40

CPC classification number: H04B1/40 ,  G11C27/026 ,  H03F3/193 ,  H03F3/45188 ,  H03F3/505 ,  H03F2200/451 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03F2203/5024 ,  H03M1/1245

Abstract: The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

公开(公告)号：US09647643B2

公开(公告)日：2017-05-09

申请号：US15231449

申请日：2016-08-08

Applicant: INPHI CORPORATION

Inventor： James Lawrence Gorecki ,  Han-Yuan Tan

IPC: H03K3/012 ,  H03K5/02 ,  G11C27/02 ,  H03F1/32 ,  H03F3/45 ,  H03M1/12 ,  H03M3/00

CPC classification number: H03K5/023 ,  G11C27/026 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03G3/20 ,  H03K3/012 ,  H03M1/1215 ,  H03M1/124 ,  H03M3/38 ,  H04B17/21

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.