知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

811 records (took 0.024 seconds)

    DYNAMIC PULSE WIDTH CONTROL SCHEME IN AMPLIFIERS
    1.
    发明公开
    DYNAMIC PULSE WIDTH CONTROL SCHEME IN AMPLIFIERS 审中-公开

    公开(公告)号：US20240213935A1

    公开(公告)日：2024-06-27

    申请号：US18088091

    申请日：2022-12-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sumit Dubey ,  Rejin Kanjavalappil Raveendranathath ,  Shaik Asif Basha

    IPC: H03F3/217 ,  H03F1/32

    CPC classification number: H03F3/2173 ,  H03F1/3205 ,  H03F2200/03 ,  H03F2200/351

    Abstract: Examples of amplifiers and components thereof are configured to adjust the OFF-pulse widths of a high-duty cycle pulse width modulated (PWM) output signal and the ON-pulse widths of a low-duty cycle PWM output signal. Such control is carried out using high- and low-side (HS and LS) detectors. The HS detector coupled to the control terminal of an HS transistor detects when the gate-to-source voltage (Vgs) of the HS transistor drops below a threshold and outputs an HS detection signal to adjust the OFF-pulse widths of the high-duty cycle PWM output signal. An LS detector coupled to the control terminal of an LS transistor detects when the Vgs of the LS transistor drops below the threshold and outputs a LS detection signal to adjust the ON-pulse widths of the low-duty cycle PWM output signal.

    PIECEWISE CONDUCTANCE NETWORK FOR RF SWITCH ON-STATE LINEARIZATION
    3.
    发明公开
    PIECEWISE CONDUCTANCE NETWORK FOR RF SWITCH ON-STATE LINEARIZATION 审中-公开

    公开(公告)号：US20240154578A1

    公开(公告)日：2024-05-09

    申请号：US18385029

    申请日：2023-10-30

    Applicant: Qorvo US, Inc.

    Inventor： Adnan Zolj ,  Jinsung Choi

    IPC: H03F1/32 ,  H03F3/45 ,  H03K17/16

    CPC classification number: H03F1/3205 ,  H03F3/45183 ,  H03K17/162 ,  H03F2200/451

    Abstract: A conductance network is disclosed for switching circuitry. In some embodiments, the conductance network includes a first conductance stage and a second conductance stage. The first conductance stage is configured to define a first voltage-to-current response such that the first voltage-to-current response defines a first deadband region between a first pair of quasi-quadratic or quasi-linear regions. The second conductance stage is configured to define a second voltage-to-current response such that the second voltage-to-current response defines a second deadband region between a second pair of quasi-quadratic or quasi-linear regions, wherein the second deadband region is wider than the first deadband region.

    Differential Mode and Common Mode Distortion Cancellation Circuitry
    5.
    发明公开
    Differential Mode and Common Mode Distortion Cancellation Circuitry 审中-公开

    公开(公告)号：US20240072735A1

    公开(公告)日：2024-02-29

    申请号：US17894065

    申请日：2022-08-23

    Applicant: Apple Inc.

    Inventor： Omar E Elaasar

    IPC: H03F1/32

    CPC classification number: H03F1/3211 ,  H03F1/3205 ,  H03F2200/451

    Abstract: An electronic device may include wireless circuitry having one or more differential circuits. A differential circuit can include first and second input transistors, first and second degeneration components, and first and second distortion cancellation transistors cross-coupled with the first and second input transistors. The first distortion cancellation transistor can be configured to sense a voltage at the first input transistor and to produce corresponding currents for cancelling a differential mode harmonic distortion current flowing through the second input transistor and for cancelling a common mode harmonic distortion current flowing through the first input transistor. The second distortion cancellation transistor can be configured to sense a voltage at the second input transistor and to produce corresponding currents for cancelling a differential mode harmonic distortion current flowing through the first input transistor and for cancelling a common mode harmonic distortion current flowing through the second input transistor.

    EQUALIZER CIRCUIT
    6.
    发明公开
    EQUALIZER CIRCUIT 审中-公开

    公开(公告)号：US20240039495A1

    公开(公告)日：2024-02-01

    申请号：US18361078

    申请日：2023-07-28

    Applicant: ROHM CO., LTD.

    Inventor： Shinichi SAITO

    IPC: H03F3/45 ,  H03G1/00 ,  H03F1/32

    CPC classification number: H03F3/45183 ,  H03F3/45273 ,  H03G1/0088 ,  H03F1/3205

    Abstract: An equalizer circuit includes a variable gain equalizer circuit. A third transistor MN for gain adjustment is coupled between a source of a first transistor that constitutes an input differential pair of the variable gain equalizer circuit, and a first current source IB. A fourth transistor MN for gain adjustment is coupled between a source of a second transistor that constitutes the input differential pair, and a second current source IB. A first bias voltage Vb is supplied to the gates of the third transistor MN and the fourth transistor MN, so as to enable DC gain control of the variable gain equalizer circuit.

    OPERATIONAL AMPLIFIER AND ELECTRONIC SYSTEM
    9.
    发明公开
    OPERATIONAL AMPLIFIER AND ELECTRONIC SYSTEM 审中-公开

    公开(公告)号：US20230378916A1

    公开(公告)日：2023-11-23

    申请号：US18318879

    申请日：2023-05-17

    Applicant: HANGZHOU GEO-CHIP TECHNOLOGY CO., LTD.

    Inventor： Chun Geik TAN ,  Sy-Chyuan HWU ,  Ruili WU ,  Yang YANG

    IPC: H03F1/32 ,  H03F3/45

    CPC classification number: H03F1/3205 ,  H03F3/45179 ,  H03F2200/451

    Abstract: An operational amplifier, any of a pair of amplification circuits of its output-stage amplification circuit unit comprises: a first and second transistors, a capacitor and a DC bias circuit; a control electrode of the first transistor is connected with a corresponding output terminal of a preceding-stage amplification circuit unit, a first electrode thereof is connected with a first power terminal and a second electrode thereof is connected with an output terminal of an amplification circuit of the output-stage amplification circuit unit; an output terminal of the DC bias circuit is connected with a control electrode of the second transistor, a first electrode of which is connected with a second power terminal, and a second electrode thereof is connected with the output terminal; both ends of the capacitor are respectively connected with the control electrodes of the first and second transistors; and the first and second transistors are of opposite polarities.

    HIGH QUIESCENT CURRENT CONTROL
    10.
    发明公开
    HIGH QUIESCENT CURRENT CONTROL 审中-公开

    公开(公告)号：US20230246595A1

    公开(公告)日：2023-08-03

    申请号：US18298626

    申请日：2023-04-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nitin Agarwal ,  Aniruddha Roy

    IPC: H03F1/02 ,  H03F1/32

    CPC classification number: H03F1/0233 ,  H03F1/3205 ,  H03F2200/504

    Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

Patent Agency Ranking