SEMICONDUCTOR DEVICE
    1.
    发明公开

    公开(公告)号:US20240313723A1

    公开(公告)日:2024-09-19

    申请号:US18604433

    申请日:2024-03-13

    发明人: Tetsuo OOMORI

    IPC分类号: H03F3/45 G05F3/26

    CPC分类号: H03F3/45273 G05F3/267

    摘要: A semiconductor device includes: an output terminal outputting an output voltage; a bipolar transistor outputting a collector current to an output node; a bias current generation part including a first node, a first constant current source, and a first transistor connected in parallel with the first constant current source, and generating a bias current; a differential input part including a differential pair and a second node, in which the differential pair generates at the second node a control voltage according to a difference between the reference voltage and the voltage corresponding to the output voltage; and a drive part including a current supply circuit, a third node, and a second transistor controlling a potential of the third node according to the control voltage. The first transistor controls the bias current according to the control voltage.

    INTRINSIC MOS CASCODE DIFFERENTIAL INPUT PAIR

    公开(公告)号:US20240258979A1

    公开(公告)日:2024-08-01

    申请号:US18160546

    申请日:2023-01-27

    申请人: pSemi Corporation

    发明人: Rogelio CICILI

    IPC分类号: H03F3/45 H03F1/22

    摘要: Methods and devices for a cascode differential input pair with low headroom voltage and high output impedance are presented. The cascode differential input pair includes first and second input (cascode) stages, each including a common-source regular transistor in series connection with a common-gate intrinsic transistor. Sources of the regular transistors are tied, and gates of the intrinsic transistors are tied. A gate voltage to the intrinsic transistors is provided by a source voltage at the sources of the regular transistors, the source voltage based on a common mode input voltage of the cascode differential input pair. According to one aspect, the cascode differential input pair is part of a differential amplifier that includes a current source coupled to the sources of the regular transistors, and a load coupled to drains of the intrinsic transistors.

    PROGRAMMABLE GAIN AMPLIFIER
    4.
    发明公开

    公开(公告)号:US20240106403A1

    公开(公告)日:2024-03-28

    申请号:US18464551

    申请日:2023-09-11

    申请人: NXP USA, INC.

    IPC分类号: H03G1/00 H03F1/26 H03F3/45

    摘要: A programmable gain amplifier that comprises: a transconductance amplifier, a switch leakage compensation circuit and a transimpedance amplifier. The transconductance amplifier provides a transconductance amplifier current signal and includes a switchable resistance network. The switch leakage compensation circuit provides a compensation current signal and comprises a switchable compensation resistance network. The transimpedance amplifier provides the output voltage signal based on the difference between the transconductance amplifier current signal and the compensation current signal. The switchable compensation resistance network comprises a plurality of branches in parallel with each other, wherein each branch includes: a gain-mimicking switch that has a corresponding gain-setting switch in the switchable resistance network; and a leakage-current-conducting switch in series with the gain-mimicking switch. The leakage-current-conducting switch is openable and closable in accordance with the complement of a switch control signal that is used to control the gain-mimicking switch in the same branch.

    SLEW-RATE BOOST CIRCUITRY
    5.
    发明公开

    公开(公告)号:US20240088853A1

    公开(公告)日:2024-03-14

    申请号:US17931947

    申请日:2022-09-14

    IPC分类号: H03F3/45

    摘要: The techniques described herein relate to a circuit including an operational amplifier that includes a differential amplifier, a capacitor, and an output stage. The differential amplifier includes a first input and a second input. The output stage is configured to generate an output voltage. The circuit includes a slew-rate boost circuitry connected to the operational amplifier. The slew-rate boost circuitry is configured to detect a voltage differential between the first input and the second input and apply, at an output of the differential amplifier, a boost current to charge the capacitor during a period of time in which the output voltage increases or decreases to a target voltage level.

    CURRENT SENSE AMPLIFIER CIRCUIT AND TRIMMING METHOD OF OFFSET REFERRED TO INPUT VOLTAGE

    公开(公告)号:US20240063767A1

    公开(公告)日:2024-02-22

    申请号:US18365200

    申请日:2023-08-03

    IPC分类号: H03F3/45

    摘要: A current sensing amplifier circuit includes: an amplifier configured to generate an output voltage correlated with a current to-be-sensed according to a first input voltage at a first input end and a second input voltage at a second input end in a normal operation mode; and a current source circuit configured to generate a trimming current according to the first input voltage and a reference voltage in a trimming mode and to provide the trimming current to trim an offset referred to input (RTI) voltage generated by the current sensing amplifier circuit in the normal operation mode. The current source circuit is coupled between: a first resistor and a non-inverting input end, a second resistor and the output voltage, a third resistor and the non-inverting input end, or a fourth resistor and an inverting input end.

    Low dropout regulator and related method

    公开(公告)号:US11853092B2

    公开(公告)日:2023-12-26

    申请号:US18165265

    申请日:2023-02-06

    IPC分类号: G05F1/575 G05F1/59 H03F3/45

    摘要: A device is provided. The device includes an operational amplifier, an output circuit, a first capacitor, and a second capacitor. The operational amplifier is configured to generate an output according to a feedback signal. The output circuit is configured to generate a first current signal in response to a supply voltage and the output of the operational amplifier. The first current signal includes a first ripple signal. The first capacitor and the second capacitor are coupled in parallel between the operational amplifier and the output circuit. The first capacitor is configured to receive the first current signal and feedback to the operational amplifier the first ripple signal.

    TEMPERATURE TOLERANT INPUT STAGES FOR CIRCUITS

    公开(公告)号:US20230353107A1

    公开(公告)日:2023-11-02

    申请号:US17731730

    申请日:2022-04-28

    发明人: Satoshi Sakurai

    IPC分类号: H03F3/45 H03K3/0233

    CPC分类号: H03F3/45273 H03K3/0233

    摘要: Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.

    Operational amplifier
    10.
    发明授权

    公开(公告)号:US11777460B2

    公开(公告)日:2023-10-03

    申请号:US17622761

    申请日:2020-09-07

    发明人: Yiqiang Wu

    IPC分类号: H03F3/45 H03F1/02

    摘要: Disclosed is an operational amplifier, including a first-stage gain circuit, a second-stage gain circuit, and a tail current compensation circuit. The first-stage gain circuit is connected to the second-stage gain circuit, the first-stage gain circuit is provided with an input terminal, the second-stage gain circuit is provided with an output terminal. The first-stage gain circuit at least includes a tail current source, a first terminal of the tail current compensation circuit is connected to the tail current source, and a second terminal of the tail current compensation circuit is connected to the output terminal of the second-stage gain circuit. The tail current compensation circuit is configured to compensate the tail current source with an output signal of the output terminal of the second-stage gain circuit.