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    High impedance passive switched capacitor common mode feedback network
    1.
    发明授权
    High impedance passive switched capacitor common mode feedback network 有权

    公开(公告)号：US10122370B2

    公开(公告)日：2018-11-06

    申请号：US15447680

    申请日：2017-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： Debesh Bhatta ,  Jeffrey Mark Hinrichs ,  Wenjing Yin

    IPC: H03L7/089 ,  H03L7/23 ,  H03G1/00

    Abstract: A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

    Fully differential charge pump with switched-capacitor common-mode feedback
    2.
    发明授权
    Fully differential charge pump with switched-capacitor common-mode feedback 有权
    全差分电荷泵，带开关电容共模反馈

    公开(公告)号：US09496880B1

    公开(公告)日：2016-11-15

    申请号：US14826888

    申请日：2015-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Wenjing Yin ,  Jeffrey Mark Hinrichs

    IPC: H03L7/06 ,  H03L7/089 ,  H02M3/07

    CPC classification number: H03L7/0891 ,  H02M3/07 ,  H03L7/087 ,  H03L7/0895 ,  H03L7/0896

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SC-CMFB circuit.

    Abstract translation: 本公开的某些方面提供了用于实现完全差分电荷泵电路的方法和装置，其通过使用低噪声开关电容器共模反馈（CMFB）电路而不是连续的电路来消除噪声源和功率消耗源， 基于时间放大器的CMFB电路。 在本公开中呈现的全差分电荷泵电路包括连接到电荷泵的差分输出节点的开关电容器CMFB（SC-CMFB）单元，并向电荷泵提供反馈信号以控制差分的共模电压 基于参考共模电压的信号。 在某些方面，复制相位频率检测器（PFD），分频器和非重叠时钟发生器为SC-CMFB电路提供控制信号。

    Compact frequency-locked loop architecture for digital clocking
    3.
    发明授权
    Compact frequency-locked loop architecture for digital clocking 有权

    公开(公告)号：US12261612B2

    公开(公告)日：2025-03-25

    申请号：US18177445

    申请日：2023-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： John Abcarius ,  Debesh Bhatta ,  Andrew Weil ,  Robert Martin Ondris ,  Wenjing Yin

    IPC: H03L7/099

    Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

    Low-power temperature-insensitive current bias circuit
    4.
    发明授权
    Low-power temperature-insensitive current bias circuit 有权

    公开(公告)号：US10185337B1

    公开(公告)日：2019-01-22

    申请号：US15945568

    申请日：2018-04-04

    Applicant: QUALCOMM Incorporated

    Inventor： Sungmin Ock ,  Wenjing Yin ,  Xuhao Huang

    IPC: G05F1/46 ,  H03K17/687

    Abstract: A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.

    High-speed AC-coupled inverter-based buffer with replica biasing
    7.
    发明授权
    High-speed AC-coupled inverter-based buffer with replica biasing 有权
    具有复制偏置的高速交流耦合逆变器缓冲器

    公开(公告)号：US09473120B1

    公开(公告)日：2016-10-18

    申请号：US14714954

    申请日：2015-05-18

    Applicant: QUALCOMM Incorporated

    Inventor： Wenjing Yin ,  Jeffrey Mark Hinrichs

    IPC: H03B1/00 ,  H03K3/00 ,  H03K3/356

    CPC classification number: H03K3/356104 ,  H03K19/017554

    Abstract: Certain aspects of the present disclosure provide a high-speed AC-coupled inverter-based buffer, which may be used as a buffer for a voltage-controlled oscillator (VCO), for example. One example buffer for a VCO generally includes a first inverter stage having an input node configured to receive a first complementary signal of a differential pair, a second inverter stage having an input node configured to receive a second complementary signal of the differential pair, a biasing stage replicating the first inverter stage or the second inverter stage, wherein an output node of the biasing stage is connected with an input node of the biasing stage, a first impedance coupled between the input node of the first inverter stage and the input node of the biasing stage, and a second impedance coupled between the input node of the second inverter stage and the input node of the biasing stage.

    Abstract translation: 本公开的某些方面提供了例如可以用作压控振荡器（VCO）的缓冲器的高速AC耦合的基于逆变器的缓冲器。 用于VCO的一个示例缓冲器通常包括具有被配置为接收差分对的第一互补信号的输入节点的第一反相器级，具有被配置为接收差分对的第二互补信号的输入节点的第二反相器级， 其中所述偏置级的输出节点与所述偏置级的输入节点连接，所述第一阻抗耦合在所述第一反相器级的输入节点和所述第一反相器级的输入节点之间， 偏置级，以及耦合在第二逆变器级的输入节点和偏置级的输入节点之间的第二阻抗。

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