Amplifier with stacked transconducting cells in parallel and/or cascade “current mode” combining

    公开(公告)号:US12113486B2

    公开(公告)日:2024-10-08

    申请号:US17378564

    申请日:2021-07-16

    Abstract: An amplifier with stacked transconducting cells in parallel and/or cascade “current mode” combining is disclosed herein. In one or more embodiments, a method for operation of a high-voltage signal amplifier comprises inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (IRF_IN), and an RF input signal (RFIN). The method further comprises outputting, by each of the transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (IRF_OUT). In one or more embodiments, the transconducting cells are connected together in cascode for the DC supply current (Idc), are connected together in parallel (or in cascade) for the RF input signal (RFIN), and are connected together in parallel (or in cascade) for the AC RF output currents (IRF_OUT).

    Radio frequency phase shifter with variable input capacitance

    公开(公告)号:US12068724B2

    公开(公告)日:2024-08-20

    申请号:US17403595

    申请日:2021-08-16

    CPC classification number: H03F3/195 H03F1/223 H03H7/20 H03H7/38 H03F2200/204

    Abstract: Aspects of the disclosure relate to a radio frequency phase shifter. An example includes an amplification stage to produce an amplified voltage, the amplification stage having a first amplifier with a first input coupled to a first output of a hybrid coupler and a second amplifier with a complementary second input coupled to a complementary second output of the hybrid coupler. A vector modulation stage coupled to the amplification stage receives the amplified voltage and produces a modulated vector, the vector modulation stage has an in-phase section and a quadrature section to control the phase of the modulated vector in response to a phase control signal. A varactor coupled across the first input and the second input of the amplification stage adjusts the capacitance between the first input and the second input in response to a capacitance control signal.

    TWO-STAGE COMMON-MODE FEEDBACK CIRCUIT AND FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER INCLUDING THE SAME

    公开(公告)号:US20240223144A1

    公开(公告)日:2024-07-04

    申请号:US18527346

    申请日:2023-12-03

    Inventor: Yoshio Nishida

    CPC classification number: H03F3/45748 H03F1/223 H03F3/45237 H03F2203/45212

    Abstract: A two-stage common-mode feedback (CMFB) circuit and a fully differential operational amplifier are provided. The two-stage CMFB circuit includes a first CMFB circuit and a second CMFB circuit. The first CMFB circuit includes a first CMFB component that receives a first differential pair of output signals of the first amplifier and a first reference signal. The first CMFB component generates a first control signal to regulate a first common-mode voltage of the first amplifier to a first reference voltage of the first reference signal. The second CMFB circuit includes a second CMFB component that receives a second differential pair of output signals of the second amplifier and a second reference signal. The second CMFB component generates a second control signal according to a second reference signal, so as to regulate a second common-mode voltage of the second amplifier to a second reference voltage of the second reference signal.

    Integrated circuit yield improvement

    公开(公告)号:US11923807B2

    公开(公告)日:2024-03-05

    申请号:US17331436

    申请日:2021-05-26

    Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

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