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公开(公告)号：US20240345609A1
公开(公告)日：2024-10-17
申请号：US18629982
申请日：2024-04-09
发明人： Zhi-Xin Chen , Lu-An Chen
摘要： A linear power converter circuit comprising: an output transistor, wherein a gate of the output transistor is controlled by an error amplification signal for converting an input voltage into an output voltage; an error amplification circuit configured to amplify a difference between a reference voltage and a feedback voltage to generate the error amplification signal, thereby regulating the output voltage to a predetermined level, wherein the feedback voltage is related to the output voltage; and a first surge protection circuit configured to clamp the gate-source voltage of the output transistor when the slew rate of the input voltage exceeds a threshold, thereby limiting the current through the output transistor to not exceed a predetermined upper limit.
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公开(公告)号：US12112811B2
公开(公告)日：2024-10-08
申请号：US18242397
申请日：2023-09-05
发明人： Ruxin Wei
摘要： In certain aspects, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a signal pair generation circuit, and a leakage track bias generator circuit connected to the signal pair generation circuit. A gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor. A first terminal of the third transistor is connected to the first terminal of the first transistor, and a second terminal of the third transistor is connected to a second terminal of the second transistor. The signal pair generation circuit is connected to a gate terminal of the second transistor and a gate terminal of the third transistor. The leakage track bias generator circuit includes a resistor, and a first terminal of the resistor is connected to the ground.
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3.发明公开公开(公告)号：US20240319755A1
公开(公告)日：2024-09-26
申请号：US18188891
申请日：2023-03-23
发明人： Jize JIANG , Hua GUAN
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： Apparatus and methods for voltage regulation. One example circuit generally includes a first transistor having a source coupled to a Vin node and having a drain coupled to a Vout node; a second transistor having a drain coupled to a gate of the first transistor; a third transistor having a drain coupled to a source of the second transistor and having a source coupled to a reference potential node of the power supply circuit; a first amplifier having a first input coupled to a reference voltage node and having an output coupled to a gate of the third transistor, with feedback between the Vout node and a second input of the first amplifier; and a second amplifier having a first input coupled to a bias node, having a second input coupled to the source of the second transistor, and having an output coupled to a gate of the second transistor.
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公开(公告)号：US20240295890A1
公开(公告)日：2024-09-05
申请号：US18177039
申请日：2023-03-01
发明人： Adrian Lin
摘要： A low-dropout (LDO) regulator includes a voltage reference node and a one-stage differential amplifier coupled to the voltage reference node. The one-stage differential amplifier includes: a differential pair of NMOS transistors; a mirroring load comprising a first current source and a PMOS transistor; a direct feed-forward (DFF) loop formed by the PMOS transistor and its parasitic gate-to-drain capacitance during a load transient; and an indirect regulation feedback (IRF) loop formed by the differential pair of NMOS transistors, a resistor, and the PMOS transistor to provide direct current (DC) voltage regulation.
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公开(公告)号：US20240291385A1
公开(公告)日：2024-08-29
申请号：US18660420
申请日：2024-05-10
申请人： ROHM CO., LTD.
发明人： Hisashi SUGIE
CPC分类号： H02M3/07 , G05F1/468 , G05F1/565 , G05F1/575 , H02M1/0045
摘要： A linear regulator adjusts an intermediate voltage VREGOUT at an output node such that an output voltage VOUT at an output terminal approaches a first target voltage VOUT(REF1). A Dixon-type charge pump circuit enters a disable state when the output voltage VOUT is higher than a threshold voltage VTH(CP) determined to be lower than the first target voltage VOUT(REF1), outputs the intermediate voltage VREGOUT at a first input node to the output node in the disable state, enters an enable state when the output voltage VOUT is lower than the threshold voltage VTH(CP), and stabilizes the output voltage VOUT at the output terminal to a second target voltage VOUT(REF2) determined to be lower than the first target voltage VOUT(REF1) in the enable state.
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公开(公告)号：US20240288893A1
公开(公告)日：2024-08-29
申请号：US18228563
申请日：2023-07-31
摘要： Methods, apparatus, systems, and articles of manufacture are described corresponding to a voltage regulator with frequency compensation. An example circuit includes a gain stage having a first input terminal, a second input terminal, and an output terminal; a transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal of the transistor coupled to a supply voltage terminal, the second current terminal of the transistor structured to be coupled to the second input terminal of the gain stage, and the control terminal of the transistor coupled to the output terminal of the gain stage; and regulator compensation circuitry having a first terminal and a second terminal, the first terminal of the regulator compensation circuitry coupled to the output terminal of the first gain stage, the second terminal of the regulator compensation circuitry coupled to the second input terminal of the gain stage.
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7.发明公开公开(公告)号：US20240288892A1
公开(公告)日：2024-08-29
申请号：US18116205
申请日：2023-03-01
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A low dropout (LDO) voltage regulator for a transmitter driver includes a set of one or more pass transistors between a voltage input and a voltage output of the LDO voltage regulator, and a control circuit configured to receive data to be transmitted by the transmitter driver and generate control signals to gates of the set of one or more pass transistors based on the data to be transmitted by the transmitter driver.
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公开(公告)号：US20240288890A1
公开(公告)日：2024-08-29
申请号：US18173144
申请日：2023-02-23
摘要： In one example, an apparatus comprises a voltage reference circuit. The voltage reference circuit has a voltage reference terminal and includes a first circuit, a first semiconductor junction device, and a second semiconductor junction device coupled between the voltage reference terminal and a ground terminal. The first circuit is configured to generate a first voltage that increases with a temperature. The first semiconductor junction device is configured to generate a second voltage that decreases with the temperature. The second semiconductor junction device is configured to generate a third voltage that decreases with the temperature. The voltage reference circuit is configured to generate a fourth voltage between the voltage reference terminal and the ground terminal based on a sum of the first voltage and a combination of the second and third voltages.
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公开(公告)号：US20240281014A1
公开(公告)日：2024-08-22
申请号：US18654104
申请日：2024-05-03
申请人： ROHM CO., LTD.
发明人： Tatsuya OKADA
摘要： A power control device serves as a main controlling agent in a power supply device which generates an output voltage from an input voltage using an output transistor, and includes: an output feedback circuit configured to receive the output voltage or a feedback voltage corresponding to it to generate a driving signal for the output transistor; a current feedback signal generation circuit configured to generate a current feedback signal for adjusting the phase characteristics of the output feedback circuit according to an output current of the power supply device; and a delay circuit configured to delay a change in the current feedback signal in response to a change in the output current.
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公开(公告)号：US20240281012A1
公开(公告)日：2024-08-22
申请号：US18423207
申请日：2024-01-25
发明人： Chenyang GAO , Sheng LIN
摘要： An LD0 circuit having a power supply rejection function, a chip, and a communication terminal. The LD0 circuit comprises a bandgap reference module (101) provided with an intermediate frequency zero adjustment unit (109), an amplification module (102) provided with an intermediate frequency zero generation unit (105), and a power output module (103). The bandgap reference module (101) is connected to the amplification module (102), and the amplification module (102) is connected to the power output module (103). For the purpose of power supply rejection at an intermediate frequency, the intermediate frequency zero adjustment unit (109) in the bandgap reference module (101) and the intermediate frequency zero generation unit (105) in the LD0 circuit are adjusted in coordination to better optimize the intermediate frequency power supply rejection performance.
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