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公开(公告)号：US20240171145A1
公开(公告)日：2024-05-23
申请号：US18418147
申请日：2024-01-19
申请人： pSemi Corporation
发明人： Jing Li , Emre Ayranci , Miles Sanner
CPC分类号： H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G3/3052 , H03G2201/504
摘要： A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
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公开(公告)号：US11955932B2
公开(公告)日：2024-04-09
申请号：US18322166
申请日：2023-05-23
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC分类号： H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US11705873B2
公开(公告)日：2023-07-18
申请号：US17965056
申请日：2022-10-13
申请人： pSemi Corporation
发明人： Miles Sanner , Emre Ayranci
IPC分类号： H03F3/195 , H03F3/21 , H03F1/56 , H03F3/193 , H03F3/72 , H03F1/22 , H03F3/16 , H03F1/02 , H04B1/16
CPC分类号： H03F3/195 , H03F1/0211 , H03F1/223 , H03F1/56 , H03F3/16 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/111 , H03F2200/222 , H03F2200/231 , H03F2200/249 , H03F2200/267 , H03F2200/294 , H03F2200/372 , H03F2200/387 , H03F2200/391 , H03F2200/396 , H03F2200/421 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2203/7209 , H04B1/16
摘要： A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
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4.发明申请公开(公告)号：US20190020322A1
公开(公告)日：2019-01-17
申请号：US16046962
申请日：2018-07-26
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
CPC分类号： H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3052 , H03G2201/504
摘要： An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号：US10038418B1
公开(公告)日：2018-07-31
申请号：US15479173
申请日：2017-04-04
申请人： pSemi Corporation
发明人： Emre Ayranci , Miles Sanner
CPC分类号： H03G3/3036 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/72 , H03F2200/156 , H03F2200/159 , H03F2200/294 , H03F2200/451 , H03F2200/489 , H03F2200/492 , H03F2200/61 , H03F2203/7239 , H03G1/0023 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3052 , H03G2201/504
摘要： An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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公开(公告)号：US20180198429A1
公开(公告)日：2018-07-12
申请号：US15914674
申请日：2018-03-07
发明人： Makoto Tabei , Daisuke Watanabe
CPC分类号： H03G1/0035 , H03F1/223 , H03F1/301 , H03F1/56 , H03F1/565 , H03F3/193 , H03F3/245 , H03F2200/18 , H03F2200/222 , H03F2200/294 , H03F2200/301 , H03F2200/387 , H03F2200/447 , H03F2200/451 , H03F2200/492
摘要： Provided is an amplification circuit that amplifies an input signal and outputs an amplified signal. The amplification circuit includes: an amplification element that outputs the amplified signal from an output terminal thereof; an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element; a variable resistor that is connected in parallel with the inductor; and a resistance value adjusting circuit that adjusts a resistance value of the variable resistor in accordance with the temperature.
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公开(公告)号：US20180034426A1
公开(公告)日：2018-02-01
申请号：US15639397
申请日：2017-06-30
发明人： Makoto Tabei , Daisuke Watanabe
CPC分类号： H03G1/0035 , H03F1/223 , H03F1/301 , H03F1/56 , H03F1/565 , H03F3/193 , H03F3/245 , H03F2200/18 , H03F2200/222 , H03F2200/294 , H03F2200/301 , H03F2200/387 , H03F2200/447 , H03F2200/451 , H03F2200/492
摘要： Provided is an amplification circuit that amplifies an input signal and outputs an amplified signal. The amplification circuit includes: an amplification element that outputs the amplified signal from an output terminal thereof; an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element; a variable resistor that is connected in parallel with the inductor; and a resistance value adjusting circuit that adjusts a resistance value of the variable resistor in accordance with the temperature.
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公开(公告)号：US09755595B1
公开(公告)日：2017-09-05
申请号：US15130691
申请日：2016-04-15
发明人： Saihua Lin
CPC分类号： H03G1/0029 , H03F1/0261 , H03F1/30 , H03F1/301 , H03F1/302 , H03F1/303 , H03F3/193 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03G1/0088 , H03G3/001 , H03K19/21
摘要： A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.
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公开(公告)号：US09705545B2
公开(公告)日：2017-07-11
申请号：US15131894
申请日：2016-04-18
CPC分类号： H04B1/123 , H03F1/223 , H03F1/56 , H03F3/193 , H03F3/195 , H03F2200/165 , H03F2200/213 , H03F2200/249 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H04B1/44 , H04L27/14
摘要： An apparatus comprising an amplifier comprising an input, a capacitor having a capacitor first side and a capacitor second side, wherein the capacitor first side is coupled to the input, a switch having a switch first side and a switch second side, wherein the switch first side is coupled to the capacitor second side, and a transistor having a transistor gate, and a transistor source, wherein the transistor gate is coupled to the input and the capacitor first side, wherein the transistor source is coupled to the switch second side and wherein the switch is positioned directly between the capacitor second side and the transistor source.
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公开(公告)号：US20170126464A1
公开(公告)日：2017-05-04
申请号：US15357566
申请日：2016-11-21
申请人： Tensorcom, Inc.
发明人： Zaw Soe
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A receiver comprises a Low Noise Amplifier (LNA) configured to amplify an input signal and a resonant circuit coupled to the LNA. A first switch couples current from the resonant circuit to a first capacitor integrating a first voltage, wherein the first switch is enabled with a clock signal. A second switch couples current from the resonant circuit to a second capacitor integrating a second voltage, wherein the second switch is enabled with an inverse clock signal. A differential amplifier comprises a positive input for receiving the first voltage and a negative input for receiving the second voltage in order to produce a sum and a difference frequency spectrum between a signal spectrum carried within the current and a frequency of the clock signal.
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