公开(公告)号：US20230396217A1

公开(公告)日：2023-12-07

申请号：US18328987

申请日：2023-06-05

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F1/22 ,  H03F1/30 ,  H03F3/189

CPC classification number: H03F1/0227 ,  H03F1/56 ,  H03F3/193 ,  H03F1/223 ,  H03F1/301 ,  H03F3/189 ,  H03F2200/18 ,  H03F2200/453 ,  H03F2200/249

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

公开(公告)号：US20190245497A1

公开(公告)日：2019-08-08

申请号：US15887816

申请日：2018-02-02

Applicant: pSemi Corporation

Inventor： Miles Sanner ,  Emre Ayranci

IPC: H03F3/195 ,  H03F1/02

CPC classification number: H03F3/195 ,  H03F1/0211 ,  H03F1/223 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/249 ,  H03F2200/267 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/396 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2203/7209 ,  H04B1/16

Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

公开(公告)号：US20190068212A1

公开(公告)日：2019-02-28

申请号：US16110891

申请日：2018-08-23

Applicant: IMEC vzw

Inventor： Benjamin Hershberg ,  Ewout Martens ,  Jan Craninckx

IPC: H03M1/18 ,  H03F3/50 ,  G05F1/70 ,  G01R29/26 ,  H03M13/00

CPC classification number: H03M1/183 ,  G01R29/26 ,  G05F1/70 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3205 ,  H03F1/3211 ,  H03F1/3217 ,  H03F1/342 ,  H03F3/005 ,  H03F3/3028 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/129 ,  H03F2200/135 ,  H03F2200/153 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/249 ,  H03F2200/252 ,  H03F2200/27 ,  H03F2200/42 ,  H03F2200/471 ,  H03F2200/546 ,  H03F2200/78 ,  H03M13/612

Abstract: The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

公开(公告)号：US20180083579A1

公开(公告)日：2018-03-22

申请号：US15272103

申请日：2016-09-21

Applicant: Peregrine Semiconductor Corporation

Inventor： Hossein Noori ,  Chih-Chieh Cheng

IPC: H03F1/32 ,  H03F1/56 ,  H03F3/195 ,  H03G3/00 ,  H03G3/10

CPC classification number: H03F1/3205 ,  H03F1/56 ,  H03F3/195 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/211 ,  H03F2200/213 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/24 ,  H03F2200/243 ,  H03F2200/249 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/306 ,  H03F2200/312 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/417 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/495 ,  H03F2200/546 ,  H03F2200/72 ,  H03F2200/75 ,  H03G1/0029 ,  H03G1/0088 ,  H03G1/0094 ,  H03G3/001 ,  H03G3/008 ,  H03G3/10 ,  H03G2201/106 ,  H03G2201/307 ,  H03G2201/504

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

公开(公告)号：US20180083577A1

公开(公告)日：2018-03-22

申请号：US15785096

申请日：2017-10-16

Applicant: Peregrine Semiconductor Corporation

Inventor： Poojan Wagh ,  Kashish Pal

IPC: H03F1/02 ,  H03F3/193 ,  H03F1/56

CPC classification number: H03F1/0227 ,  H03F1/223 ,  H03F1/301 ,  H03F1/56 ,  H03F3/189 ,  H03F3/193 ,  H03F2200/18 ,  H03F2200/249 ,  H03F2200/453

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

公开(公告)号：US09742364B2

公开(公告)日：2017-08-22

申请号：US15144907

申请日：2016-05-03

Applicant: Infineon Technologies AG

Inventor： Nikolay Ilkov ,  Paulo Oliveira ,  Daniel Kehrer

IPC: H03F3/181 ,  H03F3/19 ,  H03F1/02 ,  H03F3/191 ,  H04B1/10

CPC classification number: H03F3/19 ,  H03F1/0261 ,  H03F3/191 ,  H03F2200/111 ,  H03F2200/249 ,  H03F2200/294 ,  H03F2200/39 ,  H03F2200/451 ,  H04B1/10

Abstract: In accordance with an embodiment, a circuit includes a low noise amplifier transistor disposed on a first integrated circuit, a single pole multi throw (SPMT) switch disposed on a second integrated circuit, and a bypass switch coupled between a control node of the low noise amplifier transistor and an output node of the low noise amplifier transistor. The SPMT switch couples a plurality of module input terminals to a control node of the low noise amplifier transistor, and the bypass switch including a first switch coupled between the control node of the low noise amplifier transistor and an intermediate node, a second switch coupled between the intermediate node and the output node of the low noise amplifier transistor, and a third switch coupled between the intermediate node and a first reference node. The first integrated circuit and the second integrated circuit are disposed on a substrate.

公开(公告)号：US20170237461A1

公开(公告)日：2017-08-17

申请号：US15211039

申请日：2016-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sri Navaneethakrishnan Easwaran

IPC: H04B1/40 ,  H04L29/08 ,  H03F3/193 ,  H03F1/02 ,  H03F3/24

CPC classification number: H04B1/40 ,  H03F1/0227 ,  H03F3/193 ,  H03F3/245 ,  H03F3/301 ,  H03F2200/18 ,  H03F2200/249 ,  H03F2200/451 ,  H04L67/12

Abstract: One example includes an amplifier system. The amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system also includes an amplifier stage that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.

公开(公告)号：US09484870B2

公开(公告)日：2016-11-01

申请号：US14638630

申请日：2015-03-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shinji Nakatsuka ,  Shigeo Imai ,  Yosuke Ogawa

IPC: H03F1/02 ,  H03F3/393 ,  H03F3/45 ,  H03F3/00 ,  H03F1/30

CPC classification number: H03F3/393 ,  H03F1/0205 ,  H03F1/26 ,  H03F1/303 ,  H03F3/005 ,  H03F3/387 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/249 ,  H03F2200/271 ,  H03F2200/312 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45248 ,  H03F2203/45514

Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.

Abstract translation: 一种装置包括：运算放大器，包括放大器部分放大信号并将放大信号发射到第一和第二节点;以及输出部分，连接到第一和第二节点并从第一和第二输出端输出信号。 该装置包括第一和第二斩波开关以及第一和第二相位补偿电容元件。 第一电容开关在第一连接状态和第二连接状态之间切换。 在第一连接状态下，第一相位补偿电容元件连接在第一节点和第一输出端之间，第二相位补偿电容元件连接在第二节点和第二输出端之间。 在第二连接状态下，第一相位补偿电容元件连接在第二节点与第二输出端之间，第二相位补偿电容元件连接在第一节点与第一输出端之间。

公开(公告)号：US09473081B2

公开(公告)日：2016-10-18

申请号：US14518967

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Antonino Scuderi ,  Aristotele Hadjichristos

IPC: H03F3/68 ,  H03F3/19 ,  H03F1/56 ,  H03F3/21 ,  H03F1/22 ,  H03F3/193 ,  H03F3/24 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03F3/19 ,  H03F1/223 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/234 ,  H03F2200/249 ,  H03F2200/252 ,  H03F2200/321 ,  H03F2200/366 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/42 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2200/522 ,  H03F2200/555 ,  H03F2200/61 ,  H03F2200/75 ,  H03F2203/21106 ,  H03F2203/21136 ,  H03F2203/21139 ,  H03F2203/21142 ,  H03F2203/21178 ,  H03F2203/7215 ,  H03F2203/7236 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/007 ,  H03G3/3042

Abstract: In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

Abstract translation: 在一个实施例中，本公开包括电路，该电路包括具有用于接收输入信号的输入的第一功率放大器级，耦合到输出节点的输出，第一功率放大器级接收时变电源电压。 电路还包括与第一功率放大器并联配置的第二功率放大器级，其具有用于接收输入信号的输入，耦合到输出节点的输出，第二功率放大器级接收时变电源电压。 当电源电压处于第一低电压范围时，第一功率放大器级的第一增益减小，并且第二功率放大器级的第二增益补偿第一低功率放大器级在第一低电压范围内的增益减小 。

公开(公告)号：US20160276989A1

公开(公告)日：2016-09-22

申请号：US14638630

申请日：2015-03-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shinji Nakatsuka ,  Shigeo Imai ,  Yosuke Ogawa

IPC: H03F3/393 ,  H03F3/45

CPC classification number: H03F3/393 ,  H03F1/0205 ,  H03F1/26 ,  H03F1/303 ,  H03F3/005 ,  H03F3/387 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/249 ,  H03F2200/271 ,  H03F2200/312 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45248 ,  H03F2203/45514

Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.

Abstract translation: 一种装置包括：运算放大器，包括放大器部分放大信号并将放大信号发射到第一和第二节点;以及输出部分，连接到第一和第二节点并从第一和第二输出端输出信号。 该装置包括第一和第二斩波开关以及第一和第二相位补偿电容元件。 第一电容开关在第一连接状态和第二连接状态之间切换。 在第一连接状态下，第一相位补偿电容元件连接在第一节点和第一输出端之间，第二相位补偿电容元件连接在第二节点和第二输出端之间。 在第二连接状态下，第一相位补偿电容元件连接在第二节点与第二输出端之间，第二相位补偿电容元件连接在第一节点与第一输出端之间。