Broadband lossless partial discharge detection and noise removal device

    公开(公告)号:US12130316B2

    公开(公告)日:2024-10-29

    申请号:US18016159

    申请日:2020-07-15

    Inventor: Kwang Sik Choi

    CPC classification number: G01R29/027 G01R23/165 G01R29/26 G01R31/14

    Abstract: There is provided a broadband lossless partial discharge detection and noise removal device which includes: a partial discharge occurrence timing pulse acquiring unit acquiring a generated timing pulse of a partial discharge signal at the beginning of generation of a partial discharge signal; a partial discharge magnitude pulse acquiring unit acquiring a magnitude pulse of the partial discharge signal; a synchronization comparing unit detecting a partial discharge digital signal determined according to whether the generated timing pulse of the partial discharge signal and the magnitude pulse are synchronized; and a partial discharge signal generating unit detecting a partial discharge pulse obtained by converting the detected partial discharge digital signal into an analog signal.

    MEASUREMENT DEVICE FOR PERFORMING MEASUREMENTS WITH RESPECT TO A DUT

    公开(公告)号:US20240219442A1

    公开(公告)日:2024-07-04

    申请号:US18512782

    申请日:2023-11-17

    CPC classification number: G01R29/26 G01R31/2837

    Abstract: A measurement device (10a) for performing measurements with respect to a device under test (13) is provided. Said measurement device (10a) comprises a port (11a) for receiving a signal from the device under test (13), a signal level modification unit (14) for modifying the corresponding level of the signal in order to form a modified signal, the signal level modification unit (14) being operable in at least a first operation mode and a second operation mode being different from the first operation mode, a receiving unit (15) for receiving and digitizing the modified signal in order to a form a digitized modified signal, and a processing unit (16).
    The signal level of the first operation mode is set, e.g. by an attenuator of the device, such the signal-to-noise-ratio is high but the receiving unit causes non-linearity effects, and the signal level of the second operation mode is set lower, e.g. by an attenuator of the device, such that the receiving unit causes essentially no non-linearity effects.

    Instrument noise correction for jitter measurements

    公开(公告)号:US11709201B2

    公开(公告)日:2023-07-25

    申请号:US17009480

    申请日:2020-09-01

    CPC classification number: G01R31/31709 G01R29/26 G01R31/31725

    Abstract: A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.

    CLOCK PHASE NOISE MEASUREMENT CIRCUIT AND METHOD

    公开(公告)号:US20230168291A1

    公开(公告)日:2023-06-01

    申请号:US17969315

    申请日:2022-10-19

    CPC classification number: G01R29/26 H03K3/0315 H03K3/037

    Abstract: A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.

    PIECEWISE ESTIMATION OF NEGATIVE SEQUENCE VOLTAGE FOR FAULT DETECTION IN ELECTRICAL SYSTEMS

    公开(公告)号:US20180321320A1

    公开(公告)日:2018-11-08

    申请号:US15586809

    申请日:2017-05-04

    Abstract: A diagnostic system configured to detect a stator winding fault in an electrical machine comprising a plurality of stator windings is provided. The diagnostic system includes a processor programmed to receive measurements of three-phase voltages and currents provided to the electrical machine, compute positive, negative, and zero sequence components of voltage and current from the three-phase voltages and currents, and identify a noise factor contribution and a stator fault contribution to the negative sequence voltage by performing a two-step initialization algorithm comprising a modified recursive least square (RLS) method, the noise factor contribution comprising unbalance in the electrical machine resulting from one or more of positive sequence current, negative sequence current, and positive sequence voltage. The processor is still further programmed to detect a stator fault in the electrical machine based on the stator fault contribution to the negative sequence voltage.

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