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1.发明授权公开(公告)号：US12047102B2
公开(公告)日：2024-07-23
申请号：US17747263
申请日：2022-05-18
发明人： Mingwei Cao
CPC分类号： H04B1/1027 , H03F3/189 , H03G3/3036 , H03M1/18 , H03F2200/294
摘要： This disclosure relates to an apparatus and a method for adjusting a level of a low-noise amplifier (LNA), a terminal device, and a network-element device. The apparatus includes a LNA, a peak-to-average power ratio (PAPR) module, and an automatic gain control (AGC). The LNA is configured to amplify a received signal to obtain a first signal, where the received signal includes out-of-band interference and a target signal. The PAPR module is configured to measure a PAPR value of the first signal. The AGC module is configured to adjust a gain level of the LNA, according to the PAPR value, a maximum-linear-input-power point of the LNA, and a strength of the first signal.
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公开(公告)号：US20240219505A1
公开(公告)日：2024-07-04
申请号：US18601300
申请日：2024-03-11
发明人： Houston Fortney
CPC分类号： G01R35/005 , G01R19/25 , G01R31/2841 , H03M1/0845 , H03M1/121 , H03M1/188
摘要： An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.
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公开(公告)号：US11991490B2
公开(公告)日：2024-05-21
申请号：US17948114
申请日：2022-09-19
申请人： Vutility, Inc.
CPC分类号： H04Q9/00 , G08C19/00 , H03M1/0617
摘要： An electricity usage monitor may include a coupling component to couple the electricity usage monitor to monitor an electrical circuit, a meter to measure electricity usage of the electrical circuit, an encoder to receive, from the meter, an electricity usage measurement to generate a measurement transmission based on the electricity usage measurement, and a communication interface configured to receive the measurement transmission from the encoder and to transmit the measurement transmission into a communication network for communication to a destination on the communication network.
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公开(公告)号：US20240162913A1
公开(公告)日：2024-05-16
申请号：US18182071
申请日：2023-03-10
申请人： SK hynix Inc.
发明人： Se Won LEE
CPC分类号： H03M1/1245 , H03M1/183
摘要： A sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. The sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.
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公开(公告)号：US20240146311A1
公开(公告)日：2024-05-02
申请号：US18404055
申请日：2024-01-04
IPC分类号： H03L7/08 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/081 , H03L7/107 , H03L7/187 , H03M1/06 , H03M1/08 , H03M1/18
CPC分类号： H03L7/0807 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/0816 , H03L7/1072 , H03L7/187 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
摘要： In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.
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公开(公告)号：US11973479B2
公开(公告)日：2024-04-30
申请号：US17508686
申请日：2021-10-22
发明人： Liuan Zhang , Yulin Tan , Jon Sweat Duster , Ning Zhang , Haigang Feng , Erkan Alpman
CPC分类号： H03G3/3005 , G11B20/10027 , H03G3/001 , H03M1/185 , G11B20/10037
摘要： Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.
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公开(公告)号：US20240080037A1
公开(公告)日：2024-03-07
申请号：US18262504
申请日：2021-02-02
发明人： Rönne REIMANN
摘要： The invention relates to the process of determining an IQ offset, in particular at low intermediate frequencies, in a receiver for electromagnetic radiation, in particular for digital data transmission. The aim of the invention is to provide a simple manner for determining the IQ offset, in particular quickly, reliably, and/or at low intermediate frequencies. According to the invention, this is achieved in particular in that the analog-digital converter is separated from the receiving devices and is electrically connected to at least one resistor by means of a switch in order to determine the IQ offset. While the analog-digital converter is connected to the resistor and not to the receiving devices, digital IQ values are obtained by means of the analog-digital converter. The digital IQ values obtained while the converter is connected to the resistor are used to determine the IQ offset.
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公开(公告)号：US20240080035A1
公开(公告)日：2024-03-07
申请号：US18455291
申请日：2023-08-24
申请人： NXP USA, INC.
发明人： Thierry Dominique Yves Cassagnes , Francesco d'Esposito , Pascal Sandrez , Olivier Tico , Simon Brule
摘要： A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.
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9.发明公开公开(公告)号：US20240019517A1
公开(公告)日：2024-01-18
申请号：US18353425
申请日：2023-07-17
发明人： Houston Fortney , Noah Faust
CPC分类号： G01R35/005 , G01R19/25 , G01R31/2841 , H03M1/0845 , H03M1/121 , H03M1/188
摘要： A measurement system includes a source unit to provide a source signal to a sample and a voltage source and/or a current source and a memory. The system also includes a measurement unit configured to acquire from the sample an measurement signal that may be responsive to the source signal and a voltage measuring unit, a current measuring unit, and/or a capacitance measuring unit, and a memory. The system also includes a control unit including a digital signal processing unit; a source converter; a measurement converter. The system further includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, the measurement converter, the source unit, and the measurement unit; a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit.
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公开(公告)号：US20240007070A1
公开(公告)日：2024-01-04
申请号：US17809908
申请日：2022-06-30
申请人： Intel Corporation
发明人： Gregory CHANCE , Peter PAWLIUK
CPC分类号： H03G3/3068 , H03M1/18 , H03G3/3089
摘要： A method and apparatus for automatic gain control (AGC). A transceiver includes an analog-to-digital converter (ADC) configured to convert a received analog signal to digital signal, a measurement circuitry configured to measure a signal level on the digital signal, an AGC controller configured to generate, based on the measured signal level, an analog gain control signal to change a gain to be applied to a received analog signal in analog domain and a digital gain control signal for digital gain compensation corresponding to the gain change in analog domain, and a digital gain compensation circuitry configured to apply the digital gain compensation based on the digital gain control signal. The digital compensation gain applied to the digital bits follows a ramp profile that is an inverse of a transient response to the gain change in analog domain.
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