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    Compensation of non-linearity at digital to analog converters
    2.
    发明授权
    Compensation of non-linearity at digital to analog converters 有权

    公开(公告)号：US09900016B1

    公开(公告)日：2018-02-20

    申请号：US15588065

    申请日：2017-05-05

    Applicant: INTEL IP CORPORATION

    Inventor： Stefan Trampitsch ,  Daniel Gruber

    IPC: H03M1/06 ,  H03M1/66

    CPC classification number: H03M1/0602 ,  H03M1/0845 ,  H03M1/66

    Abstract: An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).

    SWITCHABLE SECONDARY PLAYBACK PATH
    4.
    发明申请
    SWITCHABLE SECONDARY PLAYBACK PATH 有权

    公开(公告)号：US20160173112A1

    公开(公告)日：2016-06-16

    申请号：US15050857

    申请日：2016-02-23

    Applicant: Cirrus Logic, Inc.

    Inventor： Tejasvi Das ,  John L. Melanson

    IPC: H03M1/00 ,  H03M1/78

    CPC classification number: H03M1/002 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/662 ,  H03M1/68 ,  H03M1/70 ,  H03M1/785 ,  H03M3/32 ,  H03M3/392 ,  H03M3/414 ,  H03M3/416 ,  H03M3/50

    Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.

    Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators
    5.
    发明申请
    Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 有权
    用于消除比较器的输入电容的有源负电容电路的方法和装置

    公开(公告)号：US20160134293A1

    公开(公告)日：2016-05-12

    申请号：US14995471

    申请日：2016-01-14

    Applicant: Tensorcom, Inc.

    Inventor： Dai Dai

    IPC: H03M1/00 ,  H03M1/18 ,  H03M1/08 ,  H03H11/48 ,  H03K5/24

    CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

    Abstract: A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.

    Abstract translation: 负电容电路包括耦合到第一晶体管的漏极和第二晶体管的栅极的第一节点; 耦合到所述第二晶体管的漏极和所述第一晶体管的栅极的第二节点; 耦合在所述第一晶体管的源极和所述第二晶体管的源极之间的电容器; 耦合在电源电压和第一晶体管的源极之间的第一电流镜; 以及耦合在电源电压和第二晶体管的源极之间的第二电流镜。 该电路可被配置为在较短时间段内驱动第一和第二节点之间的差分电容性负载，从而增加差分信号的传输带宽。

    Converter with an additional DC offset and method thereof
    6.
    发明授权
    Converter with an additional DC offset and method thereof 有权
    具有附加DC偏移的转换器及其方法

    公开(公告)号：US09287888B2

    公开(公告)日：2016-03-15

    申请号：US14588816

    申请日：2015-01-02

    Applicant: Realtek Semiconductor Corp.

    Inventor： Ming-Cheng Chiang ,  Wei-Cheng Tang

    IPC: H03M1/06 ,  H03M1/08 ,  H03M1/18 ,  H03M1/70

    CPC classification number: H03M1/0845 ,  H03M1/183 ,  H03M1/70 ,  H03M3/356 ,  H03M3/422 ,  H03M3/458 ,  H03M3/50

    Abstract: A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.

    Abstract translation: 具有附加DC偏移的A转换器包括开关电路，第一电容器，多个附加电容器单元和运算放大器。 转换器使用第一附加电容器单元和具有与第一附加电容器的电容器差异的第二附加电容器单元来存储彼此具有不同极性和大小的两个电荷，并且还根据两者之间的差异产生反相DC偏移 充电以补偿DC偏移。

    Power supply noise cancelling circuit and power supply noise cancelling method
    7.
    发明授权
    Power supply noise cancelling circuit and power supply noise cancelling method 有权
    电源噪声消除电路和电源噪声消除方法

    公开(公告)号：US09240797B2

    公开(公告)日：2016-01-19

    申请号：US14657728

    申请日：2015-03-13

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Kei Shiraishi ,  Masanori Furuta ,  Junya Matsuno ,  Tetsuro Itakura

    IPC: H03M1/66 ,  H03M1/08 ,  H03M1/00

    CPC classification number: H03M1/0836 ,  H03M1/001 ,  H03M1/08 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/665 ,  H03M1/742

    Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

    Abstract translation: 根据实施例，电源噪声消除电路包括发生器，第一乘法器，减法器和数模转换器。 发生器产生正弦波信号。 第一乘法器基于正弦波信号将数字输入信号乘以数字信号以产生第一数字乘积信号。 减法器基于来自数字输入信号的第一数字乘积信号减去数字信号，以产生数字差分信号。 数模转换器对数字差分信号执行数模转换以获得模拟输出信号。

    Asynchronous to synchronous sampling using Akima algorithm
    8.
    发明授权
    Asynchronous to synchronous sampling using Akima algorithm 有权
    使用Akima算法进行异步到同步采样

    公开(公告)号：US09184761B2

    公开(公告)日：2015-11-10

    申请号：US14194236

    申请日：2014-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Abhijit A. Patki ,  Ganesan Thiagarajan ,  Udayan Dasgupta

    IPC: H03M1/12 ,  H03M1/08 ,  H03M1/18 ,  H03M1/36

    CPC classification number: H03M1/125 ,  H03M1/08 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/0854 ,  H03M1/089 ,  H03M1/124 ,  H03M1/1265 ,  H03M1/186 ,  H03M1/36

    Abstract: A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.

    Abstract translation: 一种方法，包括：在选择的同步ADC转换点之前和之后选择三个二元组; 基于先前时间异步样本的值计算三次多项式的系数，周围所选样本的异步样本之间的时间差和之前三点之间的线段的五个线性斜率 选择同步采样点，包括所选点的斜率; 在同步时刻评估三阶多项式; 基于此计算产生同步ADC值; 并且使用ADC值作为同步采样的期望电压电平，其中基于该计算生成同步ADC值。

    Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
    9.
    发明授权
    Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权
    用于消除比较器的输入电容的有源负电容电路的方法和装置

    公开(公告)号：US09124279B2

    公开(公告)日：2015-09-01

    申请号：US13602216

    申请日：2012-09-03

    Applicant: Dai Dai

    Inventor： Dai Dai

    IPC: H03H11/46 ,  H03F3/45 ,  H03M1/00 ,  H03K5/24 ,  H03M1/08 ,  H03M1/18 ,  H03H11/48

    CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

    Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

    Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 这种消除延长了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS构成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

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