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公开(公告)号：US12126353B2
公开(公告)日：2024-10-22
申请号：US17945136
申请日：2022-09-15
发明人： Wei-Cian Hong
CPC分类号： H03M1/34 , H03M1/0863 , H03M1/462 , H03M1/468
摘要： The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.
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公开(公告)号：US12047087B2
公开(公告)日：2024-07-23
申请号：US17771268
申请日：2019-10-31
摘要： An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
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公开(公告)号：US12009828B2
公开(公告)日：2024-06-11
申请号：US18143695
申请日：2023-05-05
申请人： SIGMASENSE, LLC.
发明人： Phuong Huynh
CPC分类号： H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
摘要： A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US11921139B2
公开(公告)日：2024-03-05
申请号：US16655696
申请日：2019-10-17
发明人： Jae Joon Kim , Seungmok Kim , Kyeong-Hwan Park
CPC分类号： G01R27/14 , G01R27/00 , H03F3/45179 , H03M1/34 , H03M3/04
摘要： A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.
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公开(公告)号：US20230275590A1
公开(公告)日：2023-08-31
申请号：US18143695
申请日：2023-05-05
申请人： SIGMASENSE, LLC.
发明人： Phuong Huynh
CPC分类号： H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
摘要： A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US20230246650A1
公开(公告)日：2023-08-03
申请号：US18127400
申请日：2023-03-28
申请人： SIGMASENSE, LLC.
发明人： Phuong Huynh
CPC分类号： H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
摘要： A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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7.发明公开公开(公告)号：US20230238970A1
公开(公告)日：2023-07-27
申请号：US18127817
申请日：2023-03-29
申请人： SIGMASENSE, LLC.
发明人： Phuong Huynh
CPC分类号： H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
摘要： A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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8.发明授权公开(公告)号：US11646746B2
公开(公告)日：2023-05-09
申请号：US17828147
申请日：2022-05-31
申请人： SIGMASENSE, LLC.
发明人： Phuong Huynh
CPC分类号： H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
摘要： A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US20190190535A1
公开(公告)日：2019-06-20
申请号：US16219812
申请日：2018-12-13
申请人： INVENSENSE, INC.
发明人： Vadim Tsinker
CPC分类号： H03M3/496 , H03M1/124 , H03M1/34 , H03M1/50 , H03M2201/2344
摘要： Facilitating a reduction in sensor system latency, circuit size, and current draw utilizing a group of continuous-time Nyquist rate analog-to-digital converters (ADCs) in a round-robin manner is presented herein. A sensor system can comprise a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system; a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors; a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; and a continuous-time Nyquist rate analog-to-digital converter of the group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system.
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公开(公告)号：US20190109598A1
公开(公告)日：2019-04-11
申请号：US16193748
申请日：2018-11-16
申请人： TECH IDEA CO., LTD.
发明人： Akira MATSUZAWA , Masaya NOHARA
CPC分类号： H03M1/121 , H03L7/0812 , H03L7/0816 , H03M1/123 , H03M1/1295 , H03M1/34 , H03M1/56 , H04N5/37455 , H04N5/378
摘要： A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.
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