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公开(公告)号:US20230283926A1
公开(公告)日:2023-09-07
申请号:US18197876
申请日:2023-05-16
发明人: Atsumi NIWA , Yosuke UENO , Shimon TESHIMA , Daijiro ANAI , Yoshinobu FURUSAWA , Taishin YOSHIDA , Takahiro UCHIMURA , Eiji HIRATA
IPC分类号: H04N5/335 , H01L27/146 , H03M1/12 , H03M1/56
CPC分类号: H04N25/75 , H01L27/14636 , H01L27/14621 , H04N25/134 , H04N25/778 , H01L27/14612 , H04N25/772 , H01L27/14645 , H04N25/70 , H04N2209/045 , H03M1/123 , H03M1/56 , H03M1/1295
摘要: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
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公开(公告)号:US20190109598A1
公开(公告)日:2019-04-11
申请号:US16193748
申请日:2018-11-16
申请人: TECH IDEA CO., LTD.
发明人: Akira MATSUZAWA , Masaya NOHARA
CPC分类号: H03M1/121 , H03L7/0812 , H03L7/0816 , H03M1/123 , H03M1/1295 , H03M1/34 , H03M1/56 , H04N5/37455 , H04N5/378
摘要: A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.
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公开(公告)号:US10084467B1
公开(公告)日:2018-09-25
申请号:US15861624
申请日:2018-01-03
发明人: Soon-Jyh Chang , Wen-Chia Luo , Yi-Lun Chiang , Chuo-Ming Kuo
CPC分类号: H03M1/1245 , H03M1/129 , H03M1/1295 , H03M1/38 , H03M1/46
摘要: An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.
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公开(公告)号:US10062450B1
公开(公告)日:2018-08-28
申请号:US15629057
申请日:2017-06-21
申请人: Analog Devices, Inc.
发明人: Ralph D. Moore , Scott G. Bardsley
CPC分类号: G11C27/026 , G11C27/024 , H03H19/004 , H03M1/0695 , H03M1/08 , H03M1/1245 , H03M1/1295 , H03M1/164
摘要: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.
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公开(公告)号:US20180070038A1
公开(公告)日:2018-03-08
申请号:US15258077
申请日:2016-09-07
发明人: Tomas GEURTS , Joris DE BONDT
IPC分类号: H04N5/378 , H03K19/0175 , H03M3/00 , H04N5/374
CPC分类号: H04N5/378 , H03K19/017509 , H03M1/1245 , H03M1/1295 , H03M3/496 , H04N5/374
摘要: Methods and device for a readout circuit according to various aspects of the present invention may operate in conjunction with a storage device selectively coupled to an input signal having a voltage value within a first voltage range. A comparator may compare the voltage value of the input signal to a predetermined threshold voltage. A level-shifting circuit may shift the first voltage value of the input signal to a second voltage value within a second voltage range if the first voltage value of the input signal is greater than the predetermined threshold voltage.
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公开(公告)号:US09903892B2
公开(公告)日:2018-02-27
申请号:US14480321
申请日:2014-09-08
发明人: Chuang Zhang , Nan Chen , Junmou Zhang
IPC分类号: G01R19/252 , G01R23/10 , H03M1/06 , H03M1/12 , H03M1/60
CPC分类号: G01R19/252 , G01R23/10 , H03M1/0607 , H03M1/1295 , H03M1/60
摘要: In one embodiment, a method for measuring current comprises generating a sensor current based on a current being measured. The method also comprises converting a combined current into a first frequency, wherein the combined current is a sum of the sensor current and a common-mode current, and converting the first frequency into a first count value. The method further comprises converting the common-mode current into a second frequency, converting the second frequency into a second count value, and subtracting the second count value from the first count value to obtain a current reading.
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公开(公告)号:US09774811B1
公开(公告)日:2017-09-26
申请号:US15277642
申请日:2016-09-27
发明人: Hiroaki Ebihara , Zheng Yang
CPC分类号: H04N5/378 , H03K4/502 , H03K4/56 , H03K5/249 , H03M1/129 , H03M1/1295 , H03M1/56 , H03M1/66 , H04L9/3278
摘要: Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.
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公开(公告)号:US09762257B2
公开(公告)日:2017-09-12
申请号:US15236163
申请日:2016-08-12
IPC分类号: H03M1/12 , H03M1/14 , H03M3/00 , G06F17/11 , H04R3/00 , H03F3/45 , H04R19/04 , H03F3/00 , G11C27/02
CPC分类号: H03M1/14 , G06F17/11 , G11C27/024 , H03F3/005 , H03F3/45475 , H03F3/45959 , H03F2203/45421 , H03F2203/45512 , H03F2203/45544 , H03F2203/45551 , H03M1/124 , H03M1/1295 , H03M3/458 , H03M3/496 , H04R3/00 , H04R19/04 , H04R29/004 , H04R2420/05 , H04R2499/11
摘要: An analog-to-digital converter (ADC) may include capability to sense and/or compensate for undesired effects when receiving input from a microphone. For example, a sense node may be provided between differential inputs, and that sense node separated from the differential inputs by two or more switches. The sense node may allow for a measurement of an average voltage of the differential inputs. The average voltage may be obtained activating the switches to sample the sampling capacitors coupled to the differential inputs. That average voltage may be used as common mode (CM) data. A controller may receive the CM data, along with differential mode (DM) data, and use the CM and DM data to determine undesired effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesired effects.
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公开(公告)号:US20170201702A1
公开(公告)日:2017-07-13
申请号:US15313645
申请日:2015-05-21
申请人: SONY CORPORATION
发明人: Atsumi NIWA , Yosuke UENO , Shimon TESHIMA , Daijiro ANAI , Yoshinobu FURUSAWA , Taishin YOSHIDA , Takahiro UCHIMURA , Eiji HIRATA
IPC分类号: H04N5/378 , H04N9/04 , H01L27/146 , H04N5/3745
CPC分类号: H04N5/378 , H01L27/14612 , H01L27/14621 , H01L27/14636 , H01L27/14645 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/37455 , H04N5/37457 , H04N9/045 , H04N2209/045
摘要: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
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公开(公告)号:US20160329906A1
公开(公告)日:2016-11-10
申请号:US14852104
申请日:2015-09-11
CPC分类号: G01S7/4865 , G01S7/4863 , G01S17/89 , H03M1/00 , H03M1/1245 , H03M1/1295 , H03M1/164 , H03M1/361
摘要: The disclosure provides a circuit. The circuit includes a first analog to digital converter (ADC) that generates a coarse output in response to a first input and a second input. The first ADC generates the coarse output in a differential phase. A pipeline ADC generates a differential signal in response to the coarse output, the first input and the second input. The pipeline ADC generates the differential signal in a common-mode phase. The first ADC generates a common mode signal in the common-mode phase.
摘要翻译: 本公开提供一种电路。 电路包括响应于第一输入和第二输入而产生粗略输出的第一模数转换器(ADC)。 第一个ADC在差分相位产生粗略输出。 流水线ADC响应于粗略输出(第一输入和第二输入)产生差分信号。 流水线ADC在共模相位产生差分信号。 第一个ADC在共模相位产生共模信号。
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