TIME DOMAIN A/D CONVERTER GROUP AND SENSOR DEVICE USING THE SAME

    公开(公告)号:US20190109598A1

    公开(公告)日:2019-04-11

    申请号:US16193748

    申请日:2018-11-16

    IPC分类号: H03M1/12 H03M1/34

    摘要: A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.

    Passive switched capacitor circuit for sampling and amplification

    公开(公告)号:US10062450B1

    公开(公告)日:2018-08-28

    申请号:US15629057

    申请日:2017-06-21

    IPC分类号: H03M1/12 G11C27/02 H03H19/00

    摘要: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

    ADC DESIGN FOR DIFFERENTIAL AND COMMON MODE SIGNALS
    10.
    发明申请
    ADC DESIGN FOR DIFFERENTIAL AND COMMON MODE SIGNALS 审中-公开
    ADC设计用于差分和共模信号

    公开(公告)号:US20160329906A1

    公开(公告)日:2016-11-10

    申请号:US14852104

    申请日:2015-09-11

    IPC分类号: H03M1/12 G01S7/486 G01S17/02

    摘要: The disclosure provides a circuit. The circuit includes a first analog to digital converter (ADC) that generates a coarse output in response to a first input and a second input. The first ADC generates the coarse output in a differential phase. A pipeline ADC generates a differential signal in response to the coarse output, the first input and the second input. The pipeline ADC generates the differential signal in a common-mode phase. The first ADC generates a common mode signal in the common-mode phase.

    摘要翻译: 本公开提供一种电路。 电路包括响应于第一输入和第二输入而产生粗略输出的第一模数转换器(ADC)。 第一个ADC在差分相位产生粗略输出。 流水线ADC响应于粗略输出(第一输入和第二输入)产生差分信号。 流水线ADC在共模相位产生差分信号。 第一个ADC在共模相位产生共模信号。