Level shifter
    1.
    发明授权
    Level shifter 有权
    电平移位器

    公开(公告)号:US09577616B2

    公开(公告)日:2017-02-21

    申请号:US14599664

    申请日:2015-01-19

    摘要: An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

    摘要翻译: 示例性电平移位器包括:时钟电平移位器,被配置为从输入时钟信号产生电平移位的时钟信号; 以及耦合到时钟电平移位器的开关电容器逻辑控制器。 开关电容器逻辑控制器被配置为基于数据信号和输入时钟信号来引导电平移位的时钟信号,从而提供数据信号的电平移位版本。

    Passive switched capacitor circuit for sampling and amplification

    公开(公告)号:US10062450B1

    公开(公告)日:2018-08-28

    申请号:US15629057

    申请日:2017-06-21

    IPC分类号: H03M1/12 G11C27/02 H03H19/00

    摘要: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

    ADAPTABLE RECEIVER AMPLIFIER
    3.
    发明申请

    公开(公告)号:US20170187339A1

    公开(公告)日:2017-06-29

    申请号:US15205973

    申请日:2016-07-08

    IPC分类号: H03F3/185 H03G3/30 H03F3/45

    摘要: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

    Switched capacitor multiplying digital-to-analog converter

    公开(公告)号:US10541698B1

    公开(公告)日:2020-01-21

    申请号:US16184184

    申请日:2018-11-08

    发明人: Ralph D. Moore

    IPC分类号: H03M1/00 H03M1/12 H03M1/16

    摘要: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

    LEVEL SHIFTER
    5.
    发明申请
    LEVEL SHIFTER 有权
    水平变化

    公开(公告)号:US20160211832A1

    公开(公告)日:2016-07-21

    申请号:US14599664

    申请日:2015-01-19

    IPC分类号: H03K3/356 H03K19/0185

    摘要: An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

    摘要翻译: 示例性电平移位器包括:时钟电平移位器,被配置为从输入时钟信号产生电平移位的时钟信号; 以及耦合到时钟电平移位器的开关电容器逻辑控制器。 开关电容器逻辑控制器被配置为基于数据信号和输入时钟信号来引导电平移位的时钟信号,从而提供数据信号的电平移位版本。

    Switched capacitor comparator
    6.
    发明授权

    公开(公告)号:US10911058B2

    公开(公告)日:2021-02-02

    申请号:US16746949

    申请日:2020-01-19

    发明人: Ralph D. Moore

    IPC分类号: H03M1/00 H03M1/12 H03M1/16

    摘要: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

    ADAPTABLE RECEIVER AMPLIFIER
    7.
    发明申请

    公开(公告)号:US20200321926A1

    公开(公告)日:2020-10-08

    申请号:US16829768

    申请日:2020-03-25

    摘要: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

    Open loop oscillator time-to-digital conversion

    公开(公告)号:US10454483B2

    公开(公告)日:2019-10-22

    申请号:US15332152

    申请日:2016-10-24

    摘要: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.