METHODS AND CIRCUITRY FOR IMPROVING GLOBAL SHUTTER EFFICIENCY IN BACKSIDE ILLUMINATED HIGH DYNAMIC RANGE IMAGE SENSOR PIXELS

    公开(公告)号:US20210014438A1

    公开(公告)日:2021-01-14

    申请号:US16661009

    申请日:2019-10-23

    IPC分类号: H04N5/355 H01L27/146

    摘要: An image sensor may include an array of image sensor pixels. Each pixel in the array may be a global shutter pixel having a first charge storage node configured to capture scenery information and a second charge storage node configured to capture background information generated as a result of parasitic light and dark noise signals. The first and/or second charge storage nodes may each be provided with an overflow charge storage to provide high dynamic range (HDR) functionality. The background information may be subtracted from the scenery information to cancel out the desired background signal contribution and to obtain an HDR signal with high global shutter efficiency. The charge storage nodes may be implemented as storage diode or storage gate devices. The pixels may be backside illuminated pixels with optical diffracting structures and multiple microlenses formed at the backside to distribute light equally between the two charge storage nodes.

    IMAGE SENSORS HAVING HIGH DYNAMIC RANGE FUNCTIONALITIES

    公开(公告)号:US20170366766A1

    公开(公告)日:2017-12-21

    申请号:US15184458

    申请日:2016-06-16

    摘要: The image sensor pixel may include a photodiode, a charge storage region, readout circuitry, and a transfer transistor that couples the photodiode to the charge storage region. The photodiode may generate first and second image signals during first and second exposure periods, respectively. The transfer transistor may transfer the first image signal to the charge storage region. While generating the second image signal, the readout circuitry may perform readout operations on the first image signal. Thereafter, the charge storage region may be reset to a reset voltage level. The readout circuitry may perform readout operations on the reset voltage level. Then, transfer transistor may transfer the second image signal to the charge storage region. The readout circuitry may perform readout operations on the second image signal. The readout operations on both the first and second image signals may be double sampling readouts.

    IMAGE SENSOR PIXELS HAVING SEPARATED CHARGE STORAGE REGIONS

    公开(公告)号:US20170324915A1

    公开(公告)日:2017-11-09

    申请号:US15145558

    申请日:2016-05-03

    发明人: Tomas GEURTS

    IPC分类号: H04N5/353 H04N5/372 H04N5/369

    摘要: An image sensor may include pixel having nested photosensitive regions. A pixel with nested photosensitive regions may include an inner photosensitive region that has a rectangular light collecting area. The inner photosensitive region may be formed in a substrate and may be surrounded by an outer photosensitive region. The pixel with nested photosensitive regions may include trunk circuitry and transistor circuitry. Trunk circuitry may include a voltage supply source, a charge storage node, and readout transistors. Trunk circuitry may be located in close proximity to both the inner and outer photosensitive regions. Transistor circuitry may couple the inner photosensitive region, the outer photosensitive region, and trunk circuitry to one another. Microlenses may be formed over the nested photosensitive groups. Hybrid color filters having a single color filter region over the inner photosensitive region and a portion of the outer photosensitive region may also be used.

    PIXEL CIRCUITRY WITH VOLTAGE-DOMAIN SAMPLING

    公开(公告)号:US20220264042A1

    公开(公告)日:2022-08-18

    申请号:US17649815

    申请日:2022-02-03

    摘要: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

    IMAGE SENSORS HAVING IMAGING PIXELS WITH RING-SHAPED GATES

    公开(公告)号:US20200227454A1

    公开(公告)日:2020-07-16

    申请号:US16244250

    申请日:2019-01-10

    发明人: Tomas GEURTS

    IPC分类号: H01L27/146 H04N5/355

    摘要: An image sensor may include a plurality of imaging pixels with high dynamic range. Each imaging pixel may have a photodiode, a floating diffusion region, and a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region. Each imaging pixel may also include an overflow capacitor and an overflow transistor interposed between the photodiode and the overflow capacitor. A dual conversion gain transistor may be interposed between the overflow capacitor and the floating diffusion region. To reduce noise associated with operation of the pixel, a ring-shaped conductive layer may form a gate for both the overflow transistor and the dual conversion gain transistor. This common gate may be set to an intermediate level during integration to allow charge to overflow past the overflow transistor to the overflow capacitor. The common gate may also be used to assert the dual conversion gain transistor.

    IMAGING SENSORS WITH PER-PIXEL CONTROL
    10.
    发明申请

    公开(公告)号:US20200045250A1

    公开(公告)日:2020-02-06

    申请号:US16598219

    申请日:2019-10-10

    发明人: Tomas GEURTS

    摘要: Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out.