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    PHASE SHORTING SWITCH
    2.
    发明申请
    PHASE SHORTING SWITCH 有权
    相位短路开关

    公开(公告)号：US20170047939A1

    公开(公告)日：2017-02-16

    申请号：US15236163

    申请日：2016-08-12

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Ramin Zanbaghi ,  Aaron Brennan ,  Daniel J. Allen ,  John L. Melanson

    IPC: H03M1/14 ,  G06F17/11 ,  H04R3/00 ,  H03M3/00

    CPC classification number: H03M1/14 ,  G06F17/11 ,  G11C27/024 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45959 ,  H03F2203/45421 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45551 ,  H03M1/124 ,  H03M1/1295 ,  H03M3/458 ,  H03M3/496 ,  H04R3/00 ,  H04R19/04 ,  H04R29/004 ,  H04R2420/05 ,  H04R2499/11

    Abstract: An analog-to-digital converter (ADC) may include capability to sense and/or compensate for undesired effects when receiving input from a microphone. For example, a sense node may be provided between differential inputs, and that sense node separated from the differential inputs by two or more switches. The sense node may allow for a measurement of an average voltage of the differential inputs. The average voltage may be obtained activating the switches to sample the sampling capacitors coupled to the differential inputs. That average voltage may be used as common mode (CM) data. A controller may receive the CM data, along with differential mode (DM) data, and use the CM and DM data to determine undesired effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesired effects.

    Abstract translation: 模数转换器（ADC）可以包括当从麦克风接收输入时感测和/或补偿不期望的效果的能力。 例如，可以在差分输入之间提供感测节点，并且感测节点可以由两个或更多个开关与差分输入分离。 感测节点可以允许差分输入的平均电压的测量。 可以获得平均电压来激活开关以采样耦合到差分输入的采样电容器。 该平均电压可以用作共模（CM）数据。 控制器可以与差分模式（DM）数据一起接收CM数据，并使用CM和DM数据来确定不期望的效果，例如麦克风接口处的DC或AC失配。 然后，控制器可以生成用于向差分输入施加补偿的信号，以减少或消除不期望的影响。

    Non-linearity cancellation in a dual-path ADC
    4.
    发明授权
    Non-linearity cancellation in a dual-path ADC 有权
    双路ADC中的非线性消除

    公开(公告)号：US09503112B1

    公开(公告)日：2016-11-22

    申请号：US15154769

    申请日：2016-05-13

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Ramin Zanbaghi ,  Yousof Mortazavi ,  Aaron Brennan ,  John L. Melanson

    IPC: H03M1/06 ,  H03M1/10

    CPC classification number: H03M1/0602 ,  G10L19/00 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1042 ,  H03M1/188 ,  H03M1/60

    Abstract: The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancellation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

    Abstract translation: 通过使用基于VCO的ADC用于小振幅信号并采用非线性消除来消除由基于VCO的ADC输出的信号中的非线性，可以提高双路ADC系统的整体性能。 特别地，本公开的基于VCO的双路径ADC系统可以被配置为从第一ADC接收第一数字信号和从第二ADC接收第二数字信号，其中第二数字信号比第一ADC更非线性 数字信号。 至少部分地基于第一和第二数字信号的处理，双路系统还可以被配置为确定第二数字信号的一个或多个非线性系数。 至少部分地基于所确定的一个或多个非线性系数来修改第二数字信号以生成更线性的第二数字信号。

    ANALOG-TO-DIGITAL CONVERTER (ADC) DYNAMIC RANGE ENHANCEMENT FOR VOICE-ACTIVATED SYSTEMS
    5.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER (ADC) DYNAMIC RANGE ENHANCEMENT FOR VOICE-ACTIVATED SYSTEMS 有权
    模拟数字转换器（ADC）语音激活系统的动态范围增强

    公开(公告)号：US20160314805A1

    公开(公告)日：2016-10-27

    申请号：US14696172

    申请日：2015-04-24

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Yousof Mortazavi ,  Ramin Zanbaghi ,  Aaron Brennan ,  John L. Melanson

    IPC: G10L25/78 ,  G10L15/34 ,  G10L21/034 ,  G10L15/22

    CPC classification number: G10L25/78 ,  G10L15/22 ,  G10L15/28 ,  G10L15/34 ,  G10L21/034 ,  G10L2015/223 ,  H03M1/185 ,  H03M3/49

    Abstract: The dynamic range and power efficiency of a voice-activated system may be improved by dynamically adjusting the configuration of the voice-activated system's input path. In one embodiment, a first portion of audio may be received through an input path of the voice-activated system having a first configuration. A characteristic of the first portion of audio may be determined and the input path may be adjusted to a second configuration based on the determined characteristic. A second portion of audio may then be received through the input path having the second configuration, and speech analysis may be performed on the second portion of audio.

    Abstract translation: 通过动态调整语音激活的系统的输入路径的配置，可以提高语音激活的系统的动态范围和功率效率。 在一个实施例中，可以通过具有第一配置的语音激活系统的输入路径来接收音频的第一部分。 可以确定音频的第一部分的特性，并且可以基于所确定的特性将输入路径调整到第二配置。 然后可以通过具有第二配置的输入路径接收第二部分音频，并且可以在音频的第二部分上执行语音分析。

    RING FREQUENCY DIVIDER
    7.
    发明申请
    RING FREQUENCY DIVIDER 有权
    环形分频器

    公开(公告)号：US20160344392A1

    公开(公告)日：2016-11-24

    申请号：US15159750

    申请日：2016-05-19

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： John L. Melanson ,  Yousof Mortazavi ,  Aaron Brennan

    IPC: H03K23/52 ,  H03M1/12 ,  H03L7/089 ,  H03K3/037 ,  H03K3/03 ,  H03L7/099

    CPC classification number: H03K23/54 ,  G04F10/02 ,  H03K3/0315 ,  H03K3/0372 ,  H03L7/0891 ,  H03L7/0995 ,  H03M1/50

    Abstract: A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).

    Abstract translation: 用于分频器或计数器的电路可以包括具有用于分频输入频率以获得输出频率的多个环的分频器。 第一和第二环可以包括奇数多个元件，例如逆变器，其中环的每个反相器以环形链耦合到环的另一反相器。 输入频率可以被输入到第一环的反相器的电源输入端。 第二环形反相器可以在电源输入处耦合到第一环形逆变器的输出节点，这导致第二环以由（N-1）给出的第一频率的分割速率操作，其中N是 逆变器在环。 这些电路可用于分频器和计数器，例如锁相环（PLL）和模数转换器（ADC）。

    Voltage-controlled oscillator (VCO) as first stage in an analog-to-digital converter (ADC) in combination with a digital filter for second or higher-order noise shaping
    8.
    发明授权
    Voltage-controlled oscillator (VCO) as first stage in an analog-to-digital converter (ADC) in combination with a digital filter for second or higher-order noise shaping 有权
    压控振荡器（VCO）作为模数转换器（ADC）的第一级，与数字滤波器相结合，用于第二或更高阶噪声整形

    公开(公告)号：US09397692B1

    公开(公告)日：2016-07-19

    申请号：US14801620

    申请日：2015-07-16

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Ramin Zanbaghi ,  Aaron Brennan ,  John L. Melanson

    IPC: H03M1/00 ,  H03M3/00

    CPC classification number: H03M3/438 ,  H03M1/60

    Abstract: A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog input node configured to receive an analog signal; a voltage-controlled oscillator (VCO) comprising a first input configured to receive the analog signal, wherein the voltage-controlled oscillator is configured to implement a first order noise-shaping function; a digital loop filter comprising a second input configured to receive an output of the voltage-controlled oscillator (VCO); and a digital output node configured to output a digital signal based on an output of the digital loop filter. The digital loop filter may be configured to implement at least a first order noise-shaping function, but may also implement higher order noise-shaping functions.

    Abstract translation: Δ-Σ调制模数转换器（ADC）可以通过将用于一阶滤波器的VCO与用于ADC的第二或更高阶的数字环路滤波器组合来构成。 一个这样的ADC将包括被配置为接收模拟信号的模拟输入节点; 压控振荡器（VCO），包括被配置为接收所述模拟信号的第一输入，其中所述压控振荡器被配置为实现一阶噪声整形功能; 数字环路滤波器，包括被配置为接收压控振荡器（VCO）的输出的第二输入; 以及数字输出节点，被配置为基于数字环路滤波器的输出来输出数字信号。 数字环路滤波器可以被配置为实现至少一阶噪声整形功能，但也可以实现更高阶的噪声整形功能。

    Ring frequency divider
    10.
    发明授权
    Ring frequency divider 有权
    振铃分频器

    公开(公告)号：US09595971B2

    公开(公告)日：2017-03-14

    申请号：US15159750

    申请日：2016-05-19

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Yousof Mortazavi ,  John L. Melanson ,  Aaron Brennan

    IPC: H03K23/54 ,  G04F10/02 ,  H03M1/50 ,  H03K3/03 ,  H03L7/089 ,  H03L7/099 ,  H03K3/037

    CPC classification number: H03K23/54 ,  G04F10/02 ,  H03K3/0315 ,  H03K3/0372 ,  H03L7/0891 ,  H03L7/0995 ,  H03M1/50

    Abstract: A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).

    Abstract translation: 用于分频器或计数器的电路可以包括具有用于分频输入频率以获得输出频率的多个环的分频器。 第一和第二环可以包括奇数多个元件，例如逆变器，其中环的每个反相器以环形链耦合到环的另一反相器。 输入频率可以被输入到第一环的反相器的电源输入端。 第二环形反相器可以在电源输入处耦合到第一环形逆变器的输出节点，这导致第二环以由（N-1）给出的第一频率的分割速率操作，其中N是 逆变器在环。 这些电路可用于分频器和计数器，例如锁相环（PLL）和模数转换器（ADC）。

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