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    High-current sensing scheme using drain-source voltage
    2.
    发明授权
    High-current sensing scheme using drain-source voltage 有权

    公开(公告)号：US09671438B2

    公开(公告)日：2017-06-06

    申请号：US14533950

    申请日：2014-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Chuang Zhang ,  Zhengming Fu ,  Nan Chen

    IPC: G01R19/25 ,  G01R19/32 ,  G01R19/00

    CPC classification number: G01R19/25 ,  G01R19/0092 ,  G01R19/32

    Abstract: In one embodiment, a method for measuring current is described herein. The method comprises shorting first and second inputs of an amplifying circuit to generate a first output signal, and converting the first output signal into an offset cancelation value. The method also comprises passing a current through a power switch, wherein the current generates a voltage drop across the power switch, applying the voltage drop across the first and second inputs of the amplifying circuit to generate a second output signal, and converting the second output signal into a current value. The method further comprises subtracting the offset cancelation value from the current value to generate an offset-compensated current value.

    HIGH-CURRENT SENSING SCHEME USING DRAIN-SOURCE VOLTAGE
    3.
    发明申请
    HIGH-CURRENT SENSING SCHEME USING DRAIN-SOURCE VOLTAGE 有权
    使用漏源电压的高电流感测方案

    公开(公告)号：US20160124030A1

    公开(公告)日：2016-05-05

    申请号：US14533950

    申请日：2014-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Chuang Zhang ,  Zhengming Fu ,  Nan Chen

    IPC: G01R19/25 ,  G01R19/32

    CPC classification number: G01R19/25 ,  G01R19/0092 ,  G01R19/32

    Abstract: In one embodiment, a method for measuring current is described herein. The method comprises shorting first and second inputs of an amplifying circuit to generate a first output signal, and converting the first output signal into an offset cancelation value. The method also comprises passing a current through a power switch, wherein the current generates a voltage drop across the power switch, applying the voltage drop across the first and second inputs of the amplifying circuit to generate a second output signal, and converting the second output signal into a current value. The method further comprises subtracting the offset cancelation value from the current value to generate an offset-compensated current value.

    Abstract translation: 在一个实施例中，这里描述了一种用于测量电流的方法。 该方法包括缩短放大电路的第一和第二输入以产生第一输出信号，并将第一输出信号转换成偏移消除值。 该方法还包括使电流通过电源开关，其中电流在功率开关两端产生电压降，在放大电路的第一和第二输入端施加电压降，以产生第二输出信号，并转换第二输出 信号变成当前值。 该方法还包括从当前值减去偏移消除值以产生偏移补偿电流值。

    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER
    4.
    发明申请
    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER 有权
    在同步转换器上提供死区时间调整的电路和方法

    公开(公告)号：US20160118893A1

    公开(公告)日：2016-04-28

    申请号：US14918893

    申请日：2015-10-21

    Applicant: QUALCOMM Incorporated

    Inventor： James Thomas Doyle ,  Farsheed Mahmoudi ,  Chuang Zhang ,  Zhengming Fu ,  Sassan Shahrokhinia

    IPC: H02M3/158

    CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/157 ,  H02M2001/0012 ,  H02M2001/0048 ,  Y02B70/1491

    Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

    Abstract translation: 公开了一种用于在诸如同步降压转换器的电压调节器处有效地使用电力的装置和方法。 同步降压转换器包括分别由第一控制信号和第二控制信号操作的第一开关和第二开关，其中第一和第二控制信号具有相应的相位差。 逻辑电路针对第一控制信号和第二控制信号之间的相位差的迭代变化来测量输入脉宽调制（PWM）信号的占空比。 逻辑电路选择与PWM信号的最小值相对应的相位差，从而优化同步降压转换器的死区时间。 逻辑电路可以包括数字脉宽调制器。

    CIRCUITS AND METHODS PROVIDING HIGH EFFICIENCY OVER A WIDE RANGE OF LOAD VALUES
    7.
    发明申请
    CIRCUITS AND METHODS PROVIDING HIGH EFFICIENCY OVER A WIDE RANGE OF LOAD VALUES 有权
    通过宽范围的负载值提供高效率的电路和方法

    公开(公告)号：US20160118895A1

    公开(公告)日：2016-04-28

    申请号：US14863269

    申请日：2015-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Farsheed Mahmoudi ,  James Thomas Doyle ,  Chuang Zhang ,  Zhengming Fu

    IPC: H02M3/158 ,  G06F1/32

    CPC classification number: H02M3/1584 ,  G06F1/3296 ,  H02M1/088 ,  H02M3/157 ,  H02M2001/0048 ,  H02M2001/0054 ,  Y02B70/1491

    Abstract: An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.

    Abstract translation: 公开了一种用于在具有同步降压转换器的反馈回路中提供有效操作的装置和方法。 同步降压转换器包括多个单独可选择的相位，其中每个相位具有多个可单独选择和并联的开关支路。 电路存储将多个不同负载值与各自配置设置相关联的信息，每个配置设置定义多个相位和多个开关支路。 当负载变化时，电路测量负载并选择适当的配置设置。 该电路应用所选配置设置来操作降压转换器中的相数和多个并联开关支路。

    CIRCUITS AND METHODS FOR CONTROLLING A THREE-LEVEL BUCK CONVERTER
    8.
    发明申请
    CIRCUITS AND METHODS FOR CONTROLLING A THREE-LEVEL BUCK CONVERTER 有权
    用于控制三电平转换器的电路和方法

    公开(公告)号：US20160118887A1

    公开(公告)日：2016-04-28

    申请号：US14630362

    申请日：2015-02-24

    Applicant: QUALCOMM Incorporated

    Inventor： Chuang Zhang ,  James Thomas Doyle ,  Farsheed Mahmoudi ,  Amirali Shayan Arani

    IPC: H02M3/158

    CPC classification number: H02M3/158 ,  H02M1/126 ,  H02M3/07 ,  H02M7/483 ,  H02M2003/072

    Abstract: A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.

    Abstract translation: 一种电路，包括：用于三电平降压转换器的控制系统，所述三电平降压转换器包括多个输入开关，每个输入开关接收多个不同的脉宽调制信号中的一个，所述控制系统包括：第一 时钟信号和第二时钟信号，所述第二时钟信号是所述第一时钟信号的相移版本; 斜坡发生电路接收第一和第二时钟信号并分别从第一和第二时钟信号产生第一和第二斜坡信号; 接收所述第一斜坡信号并从其产生所述脉冲宽度调制信号中的第一个信号的第一比较电路; 以及第二比较电路，接收所述第二斜坡信号并从其产生所述脉冲宽度调制信号中的第二个。

    Circuits and Methods Providing Three-Level Signals At A Synchronous Buck Converter
    9.
    发明申请
    Circuits and Methods Providing Three-Level Signals At A Synchronous Buck Converter 有权
    在同步降压转换器中提供三电平信号的电路和方法

    公开(公告)号：US20160380543A1

    公开(公告)日：2016-12-29

    申请号：US15248267

    申请日：2016-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chuang Zhang ,  James Thomas Doyle ,  Farsheed Mahmoudi ,  Amirali Shayan Arani

    IPC: H02M3/158 ,  H02M1/14

    CPC classification number: H02M3/158 ,  H02M1/14 ,  H02M7/483 ,  H02M2003/072

    Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

    Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器进行充电和放电 电容器 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。

    CIRCUITS AND METHODS PROVIDING THREE-LEVEL SIGNALS AT A SYNCHRONOUS BUCK CONVERTER
    10.
    发明申请
    CIRCUITS AND METHODS PROVIDING THREE-LEVEL SIGNALS AT A SYNCHRONOUS BUCK CONVERTER 有权
    在同步转换器上提供三级信号的电路和方法

    公开(公告)号：US20160118886A1

    公开(公告)日：2016-04-28

    申请号：US14630318

    申请日：2015-02-24

    Applicant: QUALCOMM Incorporated

    Inventor： Chuang Zhang ,  James Thomas Doyle ,  Farsheed Mahmoudi ,  Amirali Shayan Arani

    IPC: H02M3/158

    CPC classification number: H02M3/158 ,  H02M1/14 ,  H02M7/483 ,  H02M2003/072

    Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

    Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器进行充电和放电 电容器 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。

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