PHASE FREQUENCY DETECTOR-BASED HIGH-PRECISION FEEDBACK FREQUENCY MEASUREMENT APPARATUS AND METHOD

    公开(公告)号:US20230092014A1

    公开(公告)日:2023-03-23

    申请号:US17816866

    申请日:2022-08-02

    IPC分类号: G01R23/10

    摘要: A phase frequency detector-based high-precision feedback frequency measurement apparatus and method: a Field Programmable Gate Array (FGPA) roughly measures a frequency fx of a measured time-frequency pulse by an equal-precision frequency measurement method; a Direct Digital Synthesizer (DDS) automatically synthesizes a frequency fx’ according to the fx roughly measured by the FPGA; the fx and the fx’ are sent to a phase frequency detector for performing phase frequency detection and then sent to the FPGA after passing through a charge pump, a low-pass filter circuit, and an (Analogue-to-Digital) A/D converter; the FPGA processes a frequency difference obtained by the phase frequency detector and then transmits the processed frequency difference to the DDS to form a negative feedback frequency measurement system so that the DDS continuously adjusts the fx’ according to a frequency difference measurement result until the output of the DDS is stable. Therefore, precise measurement of the time-frequency pulse to be measured is realized.

    OSCILLATION DETECTOR AND OPERATING METHOD THEREOF

    公开(公告)号:US20230034874A1

    公开(公告)日:2023-02-02

    申请号:US17873795

    申请日:2022-07-26

    IPC分类号: G01R23/10

    摘要: An oscillation detector includes an amplitude variation detection circuit configured to generate a first pulse signal by comparing levels of voltages with each other, a frequency variation detection circuit configured to generate a second pulse signal by filtering the first pulse signal and allowing to pass a frequency component that is less than or equal to a certain frequency among frequency components of the first pulse signal, and a time variation detection circuit configured to output an oscillation detection signal when the second pulse signal has consecutive pulses for a period of time.

    FREQUENCY COUNTER CIRCUIT FOR DETECTING TIMING VIOLATIONS

    公开(公告)号:US20210255661A1

    公开(公告)日:2021-08-19

    申请号:US17246259

    申请日:2021-04-30

    摘要: A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

    ANOMALY DETECTION APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM

    公开(公告)号:US20210247427A1

    公开(公告)日:2021-08-12

    申请号:US17270899

    申请日:2018-08-30

    申请人: NEC Corporation

    IPC分类号: G01R23/10 G01R23/14 G01R23/18

    摘要: Provided a method comprising: obtaining waveform data sets of a periodic electric waveform signal, with a length set to one cycle time; calculating a frequency spectrum for each waveform data set; extracting and separating odd and even frequency harmonics to create odd and even frequency harmonic matrices on which a canonical correlation analysis (CCA) being applied to obtain CCA features; performing linear transformation on the CCA features to obtain linear transformed features; generating a model based on the linear transformed features; performing magnitude quantization of frequency spectrums of waveform data sets to identify normal and anomalous waveform signals.

    FREQUENCY SYNTHESIZER OUTPUT CYCLE COUNTER INCLUDING RING ENCODER

    公开(公告)号:US20200041551A1

    公开(公告)日:2020-02-06

    申请号:US16597612

    申请日:2019-10-09

    IPC分类号: G01R23/02 G01R23/10

    摘要: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.