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公开(公告)号：US20210313994A1
公开(公告)日：2021-10-07
申请号：US16840642
申请日：2020-04-06
摘要： A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals, each index value corresponding to a phase difference between the master sampling clock phase and a given sampling clock phase associated with a corresponding early edge detection signal. The index logic transfers the generated index values to a master phase transfer logic unit. Phase adjust logic adjusts the master clock phase based on a selected one of the generated index values.
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公开(公告)号：US10972119B1
公开(公告)日：2021-04-06
申请号：US16875759
申请日：2020-05-15
发明人： Jeffrey Alan Fredenburg , Yuxiang Mu , Noman Hai
摘要： An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.
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公开(公告)号：US10713409B2
公开(公告)日：2020-07-14
申请号：US16351366
申请日：2019-03-12
发明人： Jeffrey Fredenburg , Muhammad Faisal , David M. Moore , Ramin Shirani , Yu Huang
IPC分类号： G06F9/455 , G06F17/50 , G06F30/392 , G06F30/3312 , G06F119/12 , G06F119/18
摘要： An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.
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4.发明授权公开(公告)号：US10594323B2
公开(公告)日：2020-03-17
申请号：US16006927
申请日：2018-06-13
摘要： A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.
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公开(公告)号：US20240250673A1
公开(公告)日：2024-07-25
申请号：US18419096
申请日：2024-01-22
IPC分类号： H03K5/14 , G01R31/317 , G06F1/08 , H03K5/00 , H03L7/081
CPC分类号： H03K5/14 , G01R31/31727 , G06F1/08 , H03L7/0812 , H03K2005/00058
摘要： A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.
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公开(公告)号：US11496139B2
公开(公告)日：2022-11-08
申请号：US17246232
申请日：2021-04-30
发明人： Xiao Wu , Jeffrey Fredenburg
摘要： A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.
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公开(公告)号：US20210258015A1
公开(公告)日：2021-08-19
申请号：US16875790
申请日：2020-05-15
发明人： Jeffrey Alan Fredenburg , Yuxiang Mu , Noman Hai
IPC分类号： H03M1/10
摘要： A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.
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8.发明申请公开(公告)号：US20200304131A1
公开(公告)日：2020-09-24
申请号：US16840626
申请日：2020-04-06
摘要： A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.
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9.发明申请公开(公告)号：US20190386663A1
公开(公告)日：2019-12-19
申请号：US16006927
申请日：2018-06-13
摘要： A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.
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10.发明申请公开(公告)号：US20180181684A1
公开(公告)日：2018-06-28
申请号：US15390360
申请日：2016-12-23
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5027 , G06F17/5031 , G06F2217/06 , G06F2217/12
摘要： A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.
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