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    Time-Interleaved ADC
    2.
    发明公开
    Time-Interleaved ADC 审中-公开

    公开(公告)号：US20240007120A1

    公开(公告)日：2024-01-04

    申请号：US18253530

    申请日：2020-11-27

    Applicant: Nippon Telegraph And Telephone Corporation

    Inventor： Naoki Terao ,  Munehiko Nagatani ,  Hideyuki Nosaka

    IPC: H03M1/12

    CPC classification number: H03M1/1245 ,  H03M1/121

    Abstract: A time interleaved ADC includes sub-ADCs that sample an analog input signal at a timing synchronized with a clock signal to convert the analog input signal into a digital output signal, delay circuits that apply a time difference to the analog input signal such that the analog input signal is input to each of the sub-ADCs with a delay of a first delay time in an arrangement order of the sub-ADCs, and delay circuits that apply a time difference to the clock signal such that the clock signal is input to each of the sub-ADCs with a delay of a second delay time in the arrangement order of the sub-ADCs.

    ELECTRONIC DEVICES CONVERTING INPUT SIGNALS TO DIGITAL VALUE AND OPERATING METHODS OF ELECTRONIC DEVICES
    4.
    发明公开
    ELECTRONIC DEVICES CONVERTING INPUT SIGNALS TO DIGITAL VALUE AND OPERATING METHODS OF ELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20230291412A1

    公开(公告)日：2023-09-14

    申请号：US17974703

    申请日：2022-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

    IPC: H03M1/18 ,  H03M1/48 ,  H03M1/12

    CPC classification number: H03M1/186 ,  H03M1/121 ,  H03M1/48

    Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

    CALIBRATION METHOD, CALIBRATION APPARATUS, TIME-INTERLEAVED ADC, ELECTRONIC DEVICE, AND READABLE MEDIUM
    5.
    发明公开
    CALIBRATION METHOD, CALIBRATION APPARATUS, TIME-INTERLEAVED ADC, ELECTRONIC DEVICE, AND READABLE MEDIUM 审中-公开

    公开(公告)号：US20230231565A1

    公开(公告)日：2023-07-20

    申请号：US17998801

    申请日：2021-05-27

    Applicant: ZTE CORPORATION

    Inventor： Xin LUO

    IPC: H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/1009 ,  H03M1/121

    Abstract: The present disclosure relates to communication devices and provides a method and apparatus for calibrating a sampling timing skew between time-interleaved analog to digital converter (ADC) channels, a time-interleaved ADC, an electronic device, and a computer readable medium. The time-interleaved ADC includes multiple ADC channels. The method includes: calculating, for every two adjacent channels, a correlation value between digital signals of two adjacent channels, according to the digital signals output by every two adjacent channels; calculating a timing skew adjustment amount corresponding to a sampling timing skew of each of the channels relative to a reference channel according to the correlation value corresponding to every two adjacent channels, the reference channel being any designated channel among the plurality of channels; and calibrating the sampling timing skew of each of the channels relative to the reference channel according to the timing skew adjustment amount corresponding to each of the channels.

    TIME DOMAIN A/D CONVERTER GROUP AND SENSOR DEVICE USING THE SAME
    7.
    发明申请
    TIME DOMAIN A/D CONVERTER GROUP AND SENSOR DEVICE USING THE SAME 审中-公开

    公开(公告)号：US20190109599A1

    公开(公告)日：2019-04-11

    申请号：US16194844

    申请日：2018-11-19

    Applicant: TECH IDEA CO., LTD.

    Inventor： Akira Matsuzawa ,  Masaya Nohara

    IPC: H03M1/12 ,  H03M1/34 ,  H03L7/081

    CPC classification number: H03M1/121 ,  H03L7/0812 ,  H03L7/0816 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/34 ,  H03M1/56 ,  H04N5/37455 ,  H04N5/378

    Abstract: A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected.

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