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公开(公告)号：US20180164352A1
公开(公告)日：2018-06-14
申请号：US15834241
申请日：2017-12-07
申请人： Rohm Co., Ltd.
发明人： Takayuki NAKASHIMA
IPC分类号： G01R19/165 , H03K5/24 , H03K5/02
CPC分类号： G01R19/16595 , G01R19/257 , H03K5/02 , H03K5/24 , H03M1/48
摘要： The voltage variation detection circuit includes: a threshold voltage generation circuit arranged to generate a threshold voltage; a comparator arranged to compare a variation detection-target voltage and the threshold voltage to each other; and a controller arranged to control the threshold voltage generation circuit based on output of the comparator. Repeated are operations of: decreasing the threshold voltage stepwise; when the variation detection-target voltage has come to the threshold voltage or more, first increasing the threshold voltage by specified steps and then again decreasing the threshold voltage stepwise; and when the variation detection-target voltage has come to the threshold voltage or more, increasing the threshold voltage by specified steps. The controller detects a variation of the variation detection-target voltage based on control results at time points when the variation detection-target voltage comes to the threshold voltage or more.
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2.发明授权公开(公告)号：US09203422B2
公开(公告)日：2015-12-01
申请号：US13630976
申请日：2012-09-28
CPC分类号： H03M1/125 , H03M1/48 , H04R25/00 , H04R25/453 , H04R25/505 , H04R2225/43
摘要： An event-driven tracking analog to digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC non-linearity, reduces the swing and dynamic common-mode range requirement of the operational transconductance amplifier (OTA) and comparators, respectively.
摘要翻译： 提出了事件驱动跟踪模数转换器（ADC）架构。 所提出的架构对放大器和DAC的非线性灵敏度较低，分别降低了运算跨导放大器（OTA）和比较器的摆幅和动态共模范围要求。
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公开(公告)号：US08917337B2
公开(公告)日：2014-12-23
申请号：US13523137
申请日：2012-06-14
申请人： Yoshio Hagihara
发明人： Yoshio Hagihara
摘要： A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.
摘要翻译： 斜坡部分产生参考信号。 比较部分将模拟信号与参考信号进行比较，并在参考信号已满足模拟信号的预定条件的定时终止比较处理。 主计数部分执行计数操作并输出计数值。 在与第一模拟信号相对应的比较处理结束的第一定时锁存第一计数值之后，锁存部分在与对应于第二模拟信号的比较处理结束相关的第二定时处锁存第二计数值 。 基于构成保持在锁存部分中的第一计数值的位的值，顺序地计数构成在锁存部分中保留的第二计数值的位的值。
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公开(公告)号：US20120320243A1
公开(公告)日：2012-12-20
申请号：US13523137
申请日：2012-06-14
申请人： Yoshio Hagihara
发明人： Yoshio Hagihara
摘要： A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.
摘要翻译： 斜坡部分产生参考信号。 比较部分将模拟信号与参考信号进行比较，并在参考信号已满足模拟信号的预定条件的定时终止比较处理。 主计数部分执行计数操作并输出计数值。 在与第一模拟信号相对应的比较处理结束的第一定时锁存第一计数值之后，锁存部分在与对应于第二模拟信号的比较处理结束相关的第二定时处锁存第二计数值 。 基于构成保持在锁存部分中的第一计数值的位的值，顺序地计数构成在锁存部分中保留的第二计数值的位的值。
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公开(公告)号：US08085179B2
公开(公告)日：2011-12-27
申请号：US12714459
申请日：2010-02-27
申请人： Simon Hainz
发明人： Simon Hainz
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/48
摘要： Various implementations relating to analog-to-digital converters are provided. A comparator of such a circuit is used for converting different analog input signals, while analog-to-digital conversion circuitry for these conversions is implemented at least partially separately. In other implementations, a comparator is used both for analog-to-digital conversion and for comparing an input signal to a constant or non-constant value.
摘要翻译： 提供了与模数转换器有关的各种实现。 这种电路的比较器用于转换不同的模拟输入信号，而用于这些转换的模拟 - 数字转换电路至少部分地实现。 在其他实施方案中，比较器用于模数转换，并用于将输入信号与常数值或非常数值进行比较。
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公开(公告)号：US20100013691A1
公开(公告)日：2010-01-21
申请号：US12531912
申请日：2007-03-26
申请人： Jean Claude Mboli
发明人： Jean Claude Mboli
IPC分类号： H03M1/12
摘要： An analogue to digital converter (ADC) is provided which comprises an signal sampling device, a signal comparison device, and a digital signal generator. An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal.The signal sampling device may produce voltage samples or current samples of the analogue signal.
摘要翻译： 提供了一种模数转换器（ADC），其包括信号采样装置，信号比较装置和数字信号发生器。 要转换为数字信号的模拟信号被输入到ADC中，信号采样装置产生模拟信号的样本，信号比较装置接收模拟信号和模拟信号样本，进行比较并输出比较信号 ，并且数字信号发生器接收比较信号并使用它们来产生数字信号。 信号采样装置可以产生模拟信号的电压样本或电流采样。
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公开(公告)号：US20090174585A1
公开(公告)日：2009-07-09
申请号：US12381007
申请日：2009-03-06
申请人： Allan L. Swain
发明人： Allan L. Swain
CPC分类号： H03M1/48
摘要： A method for converting analog values into digital form comprises comparing a current analog sample value with an analog input value to produce an outcome, generating a count value based on the outcome, the count value increasing upon successive like outcomes and being reset to an initial count value upon successive unlike outcomes, adding or subtracting the count value to/from a current digital sample value to generate a next digital sample value, the adding or subtracting being based on the outcome, and converting the next digital sample value to the current analog sample value.
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公开(公告)号：US20080158036A1
公开(公告)日：2008-07-03
申请号：US12003678
申请日：2007-12-31
申请人： Chun-Seok Jeong
发明人： Chun-Seok Jeong
CPC分类号： G01K7/015 , G01K7/425 , H01L23/34 , H01L2924/0002 , H03M1/186 , H03M1/48 , H01L2924/00
摘要： An on die thermal sensor (ODTS) in a memory device includes: a band gap unit for detecting a temperature of the memory device to output a first voltage corresponding to the temperature; and an analog-to-digital converting unit for outputting a digital code having temperature information based on the first voltage, the digital code having varied resolution according to temperature ranges.
摘要翻译： 存储器件中的裸片热传感器（ODTS）包括：带隙单元，用于检测存储器件的温度以输出对应于该温度的第一电压; 以及模数转换单元，用于根据温度范围输出具有基于第一电压的温度信息的数字代码，数字代码具有不同的分辨率。
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公开(公告)号：US07382309B2
公开(公告)日：2008-06-03
申请号：US11652553
申请日：2007-01-12
申请人： Je-Kook Kim , Jun-Ho Huh , Sang-Hoon Moon
发明人： Je-Kook Kim , Jun-Ho Huh , Sang-Hoon Moon
IPC分类号： H03M1/34
CPC分类号： H03M1/48 , G01R19/255 , H03M1/50
摘要： An analog level meter and a method of measuring an analog signal level may be provided. The analog level meter may include a comparator, a duty counter, an analog level detector and/or a digital to analog converter (DAC). The comparator may compare a voltage level of the analog signal with a reference voltage and generate an up-down signal. The duty counter may count a duty value of the up-down signal. The analog level detector may output a duty error value obtained by subtracting a target duty value from the duty value of the up-down signal. The analog level meter may output the reference voltage as a measured value of the analog signal when the duty error value is a desired or predetermined value.
摘要翻译： 可以提供模拟电平表和测量模拟信号电平的方法。 模拟电平表可以包括比较器，占空计数器，模拟电平检测器和/或数模转换器（DAC）。 比较器可以将模拟信号的电压电平与参考电压进行比较，并产生上拉信号。 占空比计数器可以计数上行信号的占空比值。 模拟电平检测器可以通过从上下信号的占空比值中减去目标占空比值而输出占空比误差值。 当占空比误差值为期望值或预定值时，模拟量表可输出参考电压作为模拟信号的测量值。
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公开(公告)号：US20080042632A1
公开(公告)日：2008-02-21
申请号：US11876756
申请日：2007-10-22
申请人： Alain Chapuis , Shuyu Lei
发明人： Alain Chapuis , Shuyu Lei
CPC分类号： H02M3/1588 , H02M3/157 , H03M1/48 , Y02B70/1466
摘要： A self-tracking analog-to-digital converter includes a digital-to-analog converter (DAC) adapted to provide a variable reference voltage, a windowed flash analog-to-digital converter (ADC) adapted to provide an error signal ek corresponding to a difference between an input voltage Vi and the variable reference voltage, and digital circuitry adapted to generate suitable control signals for the DAC based on the error signal ek. More particularly, the digital circuitry includes a first digital circuit adapted to provide a first function value f(ek) in response to the error signal ek, the first function value f(ek) representing an amount of correction to be applied to the variable reference voltage. A second digital circuit is adapted to provide a counter that combines the first function value f(ek) with a previous counter state Nk to provide a next counter state Nk+1, the next counter state Nk+1 being applied as an input to the digital-to-analog converter. A third digital circuit is adapted to scale the previous counter state Nk by a factor M and combine the scaled counter state M·Nk with the error signal ek to provide a digital output value Dk representing the input voltage Vi.
摘要翻译： 自跟踪模数转换器包括适于提供可变参考电压的数模转换器（DAC），适用于提供误差信号e
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