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公开(公告)号：US20240291500A1
公开(公告)日：2024-08-29
申请号：US18584598
申请日：2024-02-22
发明人： Jung Hyup LEE , Tae Ryoung SEOL , Ji Woong CHOI
摘要： The present invention relates to a current-to-digital converter and the current-to-digital converter according to an example embodiment includes an integrator connected to a current source that outputs input current; a quantizer connected to the integrator and configured to generate a first digital output code corresponding to alternating current (AC) in the input current; a first loop circuit formed on a delta-sigma (ΔΣ) loop that connects an input terminal of the integrator and an output terminal of the quantizer; a second loop circuit formed on a truncation-noise-shaped baseline-servo (TNS-BS) loop that connects the input terminal of the integrator and the output terminal of the quantizer and configured to generate a second digital output code corresponding to direct current (DC) in the input current; and an adder configured to generate a final digital output code by adding the first digital output code and the second digital output code.
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公开(公告)号：US20230359571A1
公开(公告)日：2023-11-09
申请号：US18217230
申请日：2023-06-30
申请人： Mythic, Inc.
发明人： Laura Fick , Manar El-Chammas , Skylar Skrzyniarz , David Fick
CPC分类号： G06F13/102 , G06F1/14 , G06N3/04 , H03M1/48 , G06F9/3001 , H03M1/662
摘要： Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.
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3.发明公开公开(公告)号：US20230291412A1
公开(公告)日：2023-09-14
申请号：US17974703
申请日：2022-10-27
发明人： Kyoungjun Roh , Jaewoo Park , Myoungbo Kwak , Jejoong Woo , Junghwan Choi
摘要： An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.
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公开(公告)号：US11465511B2
公开(公告)日：2022-10-11
申请号：US16742276
申请日：2020-01-14
发明人： John Proietty , Susan Rebecca Cikanek , Bader M. Badreddine , William Reynolds , Matthew Allan Herrmann
摘要： A vehicle includes a multi-core processor having first, second, and cores and having first and second analog-to-digital converters (ADC) associated with the first and second cores, respectively. The first and second ADC are configured to convert analog phase currents to first and second digital phase current values, respectively. The multi-core processor is configured to generate first and second rotor-angle data from digital signals representing a position of the electric machine. The processor is programmed to, via the first core, estimate a first output torque of the electric machine based on the first rotor-angle data and the first digital phase current values, via the second core, estimate a second output torque based on the second rotor-angle data and the second digital phase current values, and, via the third core, command de-activation of the electric machine in response to a difference between the first and second output torques exceeding a threshold.
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公开(公告)号：US10996634B2
公开(公告)日：2021-05-04
申请号：US16040963
申请日：2018-07-20
发明人： Chih-Wei Yao , Ronghua Ni
摘要： A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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公开(公告)号：US10830798B2
公开(公告)日：2020-11-10
申请号：US15834241
申请日：2017-12-07
申请人： Rohm Co., Ltd.
发明人： Takayuki Nakashima
IPC分类号： G01R19/165 , H03K5/24 , H03K5/02 , G01R19/257 , H03M1/48
摘要： The voltage variation detection circuit includes: a threshold voltage generation circuit arranged to generate a threshold voltage; a comparator arranged to compare a variation detection-target voltage and the threshold voltage to each other; and a controller arranged to control the threshold voltage generation circuit based on output of the comparator. Repeated are operations of: decreasing the threshold voltage stepwise; when the variation detection-target voltage has come to the threshold voltage or more, first increasing the threshold voltage by specified steps and then again decreasing the threshold voltage stepwise; and when the variation detection-target voltage has come to the threshold voltage or more, increasing the threshold voltage by specified steps. The controller detects a variation of the variation detection-target voltage based on control results at time points when the variation detection-target voltage comes to the threshold voltage or more.
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公开(公告)号：US20200348626A1
公开(公告)日：2020-11-05
申请号：US16935827
申请日：2020-07-22
发明人： Chih-Wei YAO , Ronghua NI
摘要： A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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公开(公告)号：US10284219B2
公开(公告)日：2019-05-07
申请号：US16139113
申请日：2018-09-24
发明人： Rishi Soundararajan
摘要： A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
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9.发明授权公开(公告)号：US10084472B1
公开(公告)日：2018-09-25
申请号：US15909248
申请日：2018-03-01
发明人： Hiroshi Kushihara , Kazuyuki Ishibashi , Hirofumi Maruyama , Katsutoshi Toyotake , Shinichi Arai , Toshiki Muramatsu
CPC分类号： H03M1/485 , G01D3/08 , G01D5/2046 , G01D5/2073 , G01D5/24457 , G01D5/2448 , G01P3/44 , G01P3/488 , G01R31/2829 , H02K24/00 , H02P6/16
摘要： The present invention relates to a phase modulation-type redundant two-phase-output resolver, an excitation signal (100) is applied to an excitation winding (50) of an annular stator (21) having a VR-type rotor (20) disposed therein, and a two-phase output signal (101) is outputted from first and second output windings (43, 44) that are provided in the annular stator (21), the excitation winding (50) is made up of first and second excitation windings (40, 41) of mutually different phases, and the excitation signal (100) has two phases, and even in a case where a break occurs in only any one winding from among the first and second excitation windings (40, 41) and the first and second output windings (43, 44), at least a one-phase output signal can be obtained.
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10.发明申请公开(公告)号：US20180097465A1
公开(公告)日：2018-04-05
申请号：US15719474
申请日：2017-09-28
发明人： Yusuke YASUDA
IPC分类号： H02P29/024 , H02P27/08 , H03M1/48 , G01D5/20
CPC分类号： H02P29/024 , G01D3/08 , G01D5/20 , H02P27/085 , H03M1/485
摘要： A semiconductor device according to one embodiment selects one of the first and second resolver/digital converters and interrupts a supply of a power supply voltage to the other one of the first and second resolver/digital converters, and when an error is detected in the selected one of the first and second resolver/digital converters, the semiconductor device starts the supply of the voltage to the other one of the first and second resolver/digital converters, and switches the one of the first and second resolver/digital converters to the other one of the first and second resolver/digital converters.
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