知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

96 records (took 0.027 seconds)

    Apparatuses and methods for timing skew calibration
    2.
    发明授权
    Apparatuses and methods for timing skew calibration 有权

    公开(公告)号：US12235672B2

    公开(公告)日：2025-02-25

    申请号：US18363906

    申请日：2023-08-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung Maeng ,  Jaewoo Park ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: G06F1/10

    Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240395298A1

    公开(公告)日：2024-11-28

    申请号：US18794825

    申请日：2024-08-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

    Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    4.
    发明公开
    QUADRATURE ERROR CORRECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20240241802A1

    公开(公告)日：2024-07-18

    申请号：US18383350

    申请日：2023-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Park ,  Joohwan Kim ,  Jindo Byun ,  Eunseok Shin ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: G06F11/16 ,  G06F1/10

    CPC classification number: G06F11/1604 ,  G06F1/10 ,  G06F2201/805

    Abstract: The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.

    Low dropout regulator and memory device including the same
    6.
    发明授权
    Low dropout regulator and memory device including the same 有权

    公开(公告)号：US11940830B2

    公开(公告)日：2024-03-26

    申请号：US17709853

    申请日：2022-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook Jung ,  Jaewoo Park ,  Junhan Choi ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: G11C11/4074 ,  G05F1/575 ,  G11C11/4076 ,  G11C11/4093

    CPC classification number: G05F1/575 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

    Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

    High resolution phase correcting circuit and phase interpolating device
    7.
    发明授权
    High resolution phase correcting circuit and phase interpolating device 有权

    公开(公告)号：US11888486B2

    公开(公告)日：2024-01-30

    申请号：US17872527

    申请日：2022-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinook Jung ,  Jaewoo Park ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/00 ,  H03K5/01 ,  H03H11/16

    CPC classification number: H03K5/01 ,  H03H11/16 ,  H03K2005/00019

    Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

Patent Agency Ranking