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    Electronic device using homomorphic encryption and encrypted data processing method thereof
    1.
    发明授权
    Electronic device using homomorphic encryption and encrypted data processing method thereof 有权

    公开(公告)号：US11824967B2

    公开(公告)日：2023-11-21

    申请号：US17347055

    申请日：2021-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Young Jung ,  Jiyoup Kim ,  Changkyu Seol ,  Pilsang Yoon ,  Jinsoo Lim ,  Myunghoon Choi

    IPC: H04L9/00 ,  H04L9/08

    CPC classification number: H04L9/008 ,  H04L9/0819 ,  H04L9/0869 ,  H04L9/0894

    Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

    Receivers for performing reference voltage training and memory systems including the same
    2.
    发明授权
    Receivers for performing reference voltage training and memory systems including the same 有权

    公开(公告)号：US11501805B2

    公开(公告)日：2022-11-15

    申请号：US17377654

    申请日：2021-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sucheol Lee ,  Changkyu Seol ,  Byungsuk Woo

    IPC: G11C5/14 ,  G11C11/4074

    Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

    Methods of controlling operation of nonvolatile memory devices and data converters for performing the same
    3.
    发明授权
    Methods of controlling operation of nonvolatile memory devices and data converters for performing the same 有权

    公开(公告)号：US11150987B2

    公开(公告)日：2021-10-19

    申请号：US16891517

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu Seol ,  Hyejeong So ,  Kwanwoo Noh ,  Hongrak Son ,  Pilsang Yoon

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/10 ,  H03M13/13

    Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

    Nonvolatile memory device and error correction methods thereof
    5.
    发明授权
    Nonvolatile memory device and error correction methods thereof 有权
    非易失性存储器件及其纠错方法

    公开(公告)号：US09105359B2

    公开(公告)日：2015-08-11

    申请号：US13788592

    申请日：2013-03-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonghyeog Choi ,  Junjin Kong ,  Changkyu Seol ,  Hong Rak Son

    IPC: G11C29/00 ,  G11C29/50 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G11C29/50004 ,  G06F11/1048 ,  G11C2029/0411

    Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.

    Abstract translation: 提供了一种用于处理从非易失性存储器读取的数据的数据处理方法。 数据处理方法包括在存储器控制器处从非易失性存储器接收第一位数据，并且基于存储在存储器控制器中的第一位数据和第二位数据执行擦除解码。 第一位数据指示擦除的存储单元，并且在先前纠错解码期间使用读取电压读取第二位数据。

    ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAME
    6.
    发明申请
    ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20250036520A1

    公开(公告)日：2025-01-30

    申请号：US18420877

    申请日：2024-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Daewook Kim ,  Dongjin Park ,  Hyoungbae Ahn ,  Youngdon Choi ,  Junghwan Choi

    IPC: G06F11/10

    Abstract: An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

    ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD
    8.
    发明公开
    ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD 审中-公开

    公开(公告)号：US20240178863A1

    公开(公告)日：2024-05-30

    申请号：US18511740

    申请日：2023-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Daewook Kim ,  Dongjin Park ,  Youngdon Choi

    IPC: H03M13/15 ,  H03M13/27 ,  H03M13/29

    CPC classification number: H03M13/1595 ,  H03M13/2778 ,  H03M13/2927

    Abstract: A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.

    ERROR CORRECTION USING PAM4 MODULATION
    9.
    发明公开
    ERROR CORRECTION USING PAM4 MODULATION 审中-公开

    公开(公告)号：US20230396268A1

    公开(公告)日：2023-12-07

    申请号：US18055867

    申请日：2022-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Pilsang Yoon

    IPC: H03M13/09 ,  H03M13/11 ,  H03M13/45

    CPC classification number: H03M13/09 ,  H03M13/1125 ,  H03M13/45

    Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.

    Stacked neuromorphic devices and neuromorphic computing systems
    10.
    发明授权
    Stacked neuromorphic devices and neuromorphic computing systems 有权

    公开(公告)号：US11531871B2

    公开(公告)日：2022-12-20

    申请号：US16854942

    申请日：2020-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Geunyeong Yu ,  Chanho Yoon ,  Pilsang Yoon

    IPC: G06N3/04 ,  H01L25/18 ,  G06N3/063 ,  H01L25/065

    Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

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