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    Electronic device using homomorphic encryption and encrypted data processing method thereof
    1.
    发明授权
    Electronic device using homomorphic encryption and encrypted data processing method thereof 有权

    公开(公告)号：US11824967B2

    公开(公告)日：2023-11-21

    申请号：US17347055

    申请日：2021-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Young Jung ,  Jiyoup Kim ,  Changkyu Seol ,  Pilsang Yoon ,  Jinsoo Lim ,  Myunghoon Choi

    IPC: H04L9/00 ,  H04L9/08

    CPC classification number: H04L9/008 ,  H04L9/0819 ,  H04L9/0869 ,  H04L9/0894

    Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

    Methods of controlling operation of nonvolatile memory devices and data converters for performing the same
    2.
    发明授权
    Methods of controlling operation of nonvolatile memory devices and data converters for performing the same 有权

    公开(公告)号：US11150987B2

    公开(公告)日：2021-10-19

    申请号：US16891517

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu Seol ,  Hyejeong So ,  Kwanwoo Noh ,  Hongrak Son ,  Pilsang Yoon

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/10 ,  H03M13/13

    Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

    ERROR CORRECTION USING PAM4 MODULATION
    7.
    发明公开
    ERROR CORRECTION USING PAM4 MODULATION 审中-公开

    公开(公告)号：US20230396268A1

    公开(公告)日：2023-12-07

    申请号：US18055867

    申请日：2022-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Pilsang Yoon

    IPC: H03M13/09 ,  H03M13/11 ,  H03M13/45

    CPC classification number: H03M13/09 ,  H03M13/1125 ,  H03M13/45

    Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.

    Stacked neuromorphic devices and neuromorphic computing systems
    8.
    发明授权
    Stacked neuromorphic devices and neuromorphic computing systems 有权

    公开(公告)号：US11531871B2

    公开(公告)日：2022-12-20

    申请号：US16854942

    申请日：2020-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Geunyeong Yu ,  Chanho Yoon ,  Pilsang Yoon

    IPC: G06N3/04 ,  H01L25/18 ,  G06N3/063 ,  H01L25/065

    Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

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