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公开(公告)号：US20240296898A1
公开(公告)日：2024-09-05
申请号：US18399018
申请日：2023-12-28
发明人： Taehong Kwon , Daeseok Byeon
IPC分类号： G11C29/12
CPC分类号： G11C29/12005 , G11C29/12015 , G11C2029/1202
摘要： A memory device includes a memory cell array connected to a plurality of word lines, a clock generator configured to generate a clock signal, a charge pump circuit configured to generate a voltage to be provided to the plurality of word lines, based on the clock signal, a row decoder configured to provide the voltage to a selected memory block, a current generation circuit connected in parallel to a word line path through which the voltage is provided from the charge pump circuit to the row decoder and configured to generate a current flowing through the word line path for a reference time, and a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before the reference time with a second count value of the clock signal counted after the reference time.
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公开(公告)号：US20240257898A1
公开(公告)日：2024-08-01
申请号：US18425747
申请日：2024-01-29
发明人： Taehong KWON , Daeseok Byeon
IPC分类号： G11C29/00
CPC分类号： G11C29/702 , G11C29/781 , G11C29/789
摘要： A memory device is provided. The memory device includes: a first cell region provided in a first layer and including a first bit line and a first redundant bit line; a second cell region provided in a second layer and including a second bit line and a second redundant bit line; a peripheral region provided in a third layer and including first page buffers configured to be respectively connected to the first bit line and the second bit line, and a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line; and a control circuit configured to: based on the first bit line being defective, replace the first bit line with the first redundant bit line; and based on the second bit line being defective, replace the second bit line with the second redundant bit line.
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公开(公告)号：US20240145306A1
公开(公告)日：2024-05-02
申请号：US18236165
申请日：2023-08-21
发明人： Gyosoo CHOO , Daeseok Byeon , Taehong Kwon
CPC分类号： H01L21/78 , H01L24/80 , H01L24/94 , H10B43/27 , H01L2224/80895 , H01L2224/80896 , H01L2224/94
摘要： A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.
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公开(公告)号：US11901033B2
公开(公告)日：2024-02-13
申请号：US18149302
申请日：2023-01-03
发明人： Jooyong Park , Minsu Kim , Daeseok Byeon , Pansuk Kwak
IPC分类号： G11C29/00 , G06F11/20 , G11C16/04 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/12 , G11C29/02 , G11C29/52 , G11C29/42 , G11C29/24
CPC分类号： G11C29/838 , G06F11/2094 , G11C16/0483 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/349 , G11C16/3472 , G11C29/02 , G11C29/24 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/70 , G11C29/702 , G11C29/785 , G11C29/789 , G11C2029/1204
摘要： A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US11367735B2
公开(公告)日：2022-06-21
申请号：US16835484
申请日：2020-03-31
发明人： Bongsoon Lim , Daeseok Byeon
IPC分类号： H01L27/11575 , H01L27/11551 , H01L27/11582 , H01L27/11565 , H01L29/04 , H01L27/11519 , H01L27/11548
摘要： Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.
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公开(公告)号：US11342234B2
公开(公告)日：2022-05-24
申请号：US16846724
申请日：2020-04-13
发明人： Taehyo Kim , Daeseok Byeon , Chanho Kim
IPC分类号： G01R31/26 , H01L23/552 , H01L23/522 , H01L23/528 , H01L23/50 , H01L21/66 , H01L23/544 , G01N21/95
摘要： A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.
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公开(公告)号：US11302396B2
公开(公告)日：2022-04-12
申请号：US16862167
申请日：2020-04-29
发明人： Taehong Kwon , Youngsun Min , Daeseok Byeon , Kyunghwa Yun
IPC分类号： G11C8/00 , G11C16/04 , G11C16/08 , G11C16/26 , G11C16/30 , G11C16/24 , G11C16/10 , H01L27/1157
摘要： A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
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8.发明授权公开(公告)号：US11237955B2
公开(公告)日：2022-02-01
申请号：US17007501
申请日：2020-08-31
发明人： Taehyo Kim , Daeseok Byeon , Taehong Kwon , Chanho Kim , Taeyun Lee
IPC分类号： G11C16/34 , G06F12/02 , G06F12/123 , G06F12/0811 , G11C11/4091 , G11C11/408 , G11C11/4074 , G06F12/14
摘要： A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.
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公开(公告)号：US11227815B2
公开(公告)日：2022-01-18
申请号：US16827746
申请日：2020-03-24
发明人： Taehyo Kim , Chanho Kim , Daeseok Byeon
IPC分类号： H01L23/495 , H01L23/538 , H01L23/00
摘要： A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.
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公开(公告)号：US11200002B2
公开(公告)日：2021-12-14
申请号：US16918310
申请日：2020-07-01
发明人： Yonghyuk Choi , Jaeduk Yu , Sangwan Nam , Sangwon Park , Daeseok Byeon , Bongsoon Lim
IPC分类号： G06F3/00 , G06F3/06 , G11C16/08 , G11C16/24 , G11C16/04 , H01L27/11556 , H01L27/11582
摘要： A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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