公开(公告)号：US11513730B2

公开(公告)日：2022-11-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F11/00 ,  G06F3/06 ,  G05D1/00 ,  G06F13/16 ,  G11C5/02 ,  B60W50/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US11646064B2

公开(公告)日：2023-05-09

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US11237983B2

公开(公告)日：2022-02-01

申请号：US16865580

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G06F12/02 ,  G06F12/123 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F12/14

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US20220020404A1

公开(公告)日：2022-01-20

申请号：US17207398

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US11309033B2

公开(公告)日：2022-04-19

申请号：US17121015

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Youngmin Jo ,  Seungwon Lee

IPC: G11C16/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11582

Abstract: A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

公开(公告)号：US20210375347A1

公开(公告)日：2021-12-02

申请号：US17196183

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin JO ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

IPC: G11C11/4072 ,  G11C11/4099 ,  G11C11/4093 ,  G11C5/06

Abstract: A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

公开(公告)号：US20210124527A1

公开(公告)日：2021-04-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G05D1/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US11842790B2

公开(公告)日：2023-12-12

申请号：US18125260

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

公开(公告)号：US11342234B2

公开(公告)日：2022-05-24

申请号：US16846724

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Chanho Kim

IPC: G01R31/26 ,  H01L23/552 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L21/66 ,  H01L23/544 ,  G01N21/95

Abstract: A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.

公开(公告)号：US11237955B2

公开(公告)日：2022-02-01

申请号：US17007501

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G11C16/34 ,  G06F12/02 ,  G06F12/123 ,  G06F12/0811 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4074 ,  G06F12/14

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.