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公开(公告)号：US11974440B2
公开(公告)日：2024-04-30
申请号：US17219299
申请日：2021-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Inho Kang , Ansoo Park , Jeunghwan Park , Dongha Shin , Jeawon Jeong
CPC classification number: H10B43/40 , G06F3/0656 , H10B43/27 , H10B43/35
Abstract: A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.
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公开(公告)号：US11842790B2
公开(公告)日：2023-12-12
申请号：US18125260
申请日：2023-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
CPC classification number: G11C7/1039 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C7/12
Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
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3.发明公开公开(公告)号：US20240049471A1
公开(公告)日：2024-02-08
申请号：US18322040
申请日：2023-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Inho Kang , Seungyeon Kim , Jiyoung Kim , Woosung Yang , Jaeeun Lee , Kiwhan Song
IPC: H10B43/40 , H10B41/10 , H10B41/27 , H10B41/41 , H10B43/10 , H10B43/27 , H10B80/00 , H01L25/065 , H01L25/18 , H01L23/00
CPC classification number: H10B43/40 , H10B41/10 , H10B41/27 , H10B41/41 , H10B43/10 , H10B43/27 , H10B80/00 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.
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公开(公告)号：US11869579B2
公开(公告)日：2024-01-09
申请号：US17530911
申请日：2021-11-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Inho Kang , Ilhan Park , Jinyoung Chun
IPC: G11C11/4093 , G11C11/406 , G11C7/10 , G11C11/4096 , G11C11/4074 , G11C11/4094
CPC classification number: G11C11/4093 , G11C7/1039 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C11/40615
Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.
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Patent Agency Ranking
公开(公告)号：US20230223056A1
公开(公告)日：2023-07-13
申请号：US18125260
申请日：2023-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
CPC classification number: G11C16/24 , H10B80/00 , G11C16/0483
Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
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公开(公告)号：US20240105267A1
公开(公告)日：2024-03-28
申请号：US18201331
申请日：2023-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Inho Kang , Daeseok Byeon , Beakhyung Cho , Min-Hwi Kim , Yongsung Cho , Gyosoo Choo
CPC classification number: G11C16/24 , G11C16/0483 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/41 , H10B43/40 , H10B80/00 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.
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公开(公告)号：US20240055055A1
公开(公告)日：2024-02-15
申请号：US18197258
申请日：2023-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Inho Kang , Insu Kim , Jaehue Shin
CPC classification number: G11C16/24 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/26 , H01L25/0657 , H01L24/08 , H10B80/00 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.
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公开(公告)号：US11646064B2
公开(公告)日：2023-05-09
申请号：US17207398
申请日：2021-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
CPC classification number: G11C7/1039 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C7/12
Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
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公开(公告)号：US20220020404A1
公开(公告)日：2022-01-20
申请号：US17207398
申请日：2021-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
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