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    SEMICONDUCTOR DEVICE WITH CMOS INVERTER
    3.
    发明公开
    SEMICONDUCTOR DEVICE WITH CMOS INVERTER 审中-公开

    公开(公告)号：US20230178550A1

    公开(公告)日：2023-06-08

    申请号：US17937473

    申请日：2022-10-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Beomyong Hwang ,  Jihye Kwon ,  Jiyoung Kim

    IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L29/41741 ,  H01L29/7827 ,  H01L21/823871 ,  H01L21/823885

    摘要： A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.

    Three-dimensional semiconductor memory device
    5.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11296102B2

    公开(公告)日：2022-04-05

    申请号：US16858983

    申请日：2020-04-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sung-Min Hwang ,  Woosung Yang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim

    IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  G11C5/06 ,  G11C5/02

    摘要： Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

    Semiconductor memory devices
    6.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US10910378B2

    公开(公告)日：2021-02-02

    申请号：US16268748

    申请日：2019-02-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

    IPC分类号： H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

    摘要： Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

    Semiconductor device having buried gate structure and method of fabricating the same
    7.
    发明授权
    Semiconductor device having buried gate structure and method of fabricating the same 有权

    公开(公告)号：US10263084B2

    公开(公告)日：2019-04-16

    申请号：US15868620

    申请日：2018-01-11

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

    IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L27/088

    摘要： A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

    Semiconductor device and data storage system including the same
    9.
    发明授权
    Semiconductor device and data storage system including the same 有权

    公开(公告)号：US12096625B2

    公开(公告)日：2024-09-17

    申请号：US17375933

    申请日：2021-07-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yoonjo Hwang ,  Jiyoung Kim ,  Jungtae Sung ,  Junyoung Choi

    IPC分类号： H10B41/27 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528 ,  H10B43/27

    CPC分类号： H10B41/27 ,  G11C5/025 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/27

    摘要： A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.