公开(公告)号：US20250120089A1

公开(公告)日：2025-04-10

申请号：US18830677

申请日：2024-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon Lee ,  Minyong Lee ,  Junhyoung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit, and a lower insulating structure on the peripheral circuit, a cell array structure having a cell area and a peripheral connection area and including an upper insulating structure in contact with the lower insulating structure, a cell stack in the cell area on the upper insulating structure, a common source line layer on the cell stack and having a common source opening, a plurality of cell channel structures extending in a vertical direction in the cell stack and into the common source line layer, and a support structure extending in the vertical direction in the cell stack and into the common source opening, and a pad pattern extending from the peripheral connection area to the cell area on the cell array structure and overlapping the support structure in the vertical direction.

公开(公告)号：US20250126790A1

公开(公告)日：2025-04-17

申请号：US18756161

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minyong Lee ,  Jiyoung Kim ,  Sehoon Lee ,  Junhyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/40

Abstract: An example non-volatile memory device includes a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region, a mold structure including a plurality of gate electrodes being stacked in a stepped pattern in a pad region, a trench along a profile of the mold structure on the pad region, the trench including a bottom surface having a stair shape and a first sidewall on a boundary between the pad region and a wall region, a liner film on the first sidewall of the trench, a recess in the trench and exposing a pad portion of a gate electrode, a cell contact provided at the recess and connected with the pad portion, and a cover insulating layer provided at the trench. The liner film has a different etch selectivity with respect to the cover insulating layer.