公开(公告)号：US20220278121A1

公开(公告)日：2022-09-01

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US10784272B2

公开(公告)日：2020-09-22

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US09184136B2

公开(公告)日：2015-11-10

申请号：US14141947

申请日：2013-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Daeik Kim ,  Kang-Uk Kim ,  Nara Kim ,  Jemin Park ,  Kyuhyun Lee ,  Hyun-Woo Chung ,  Gyoyoung Jin ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L23/544 ,  H01L23/48 ,  H01L21/683 ,  H01L27/06 ,  H01L27/146 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。

公开(公告)号：US11616065B2

公开(公告)日：2023-03-28

申请号：US17090419

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US09607994B2

公开(公告)日：2017-03-28

申请号：US14755690

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam Kim ,  Sunyoung Park ,  Kyehee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Changhyun Cho ,  HyeongSun Hong

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/26513 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

公开(公告)号：US10861854B2

公开(公告)日：2020-12-08

申请号：US16707019

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US10535659B2

公开(公告)日：2020-01-14

申请号：US16038052

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.