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    Semiconductor device and method of fabricating the same
    4.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US09640444B2

    公开(公告)日：2017-05-02

    申请号：US14807220

    申请日：2015-07-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sang-Kyu Oh ,  Kwanyoung Chun ,  Sunyoung Park ,  Taejoong Song

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

    CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

    Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

    Semiconductor devices and methods of forming the same
    5.
    发明授权
    Semiconductor devices and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09449970B2

    公开(公告)日：2016-09-20

    申请号：US14829650

    申请日：2015-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Moo-Gyu Bae ,  Taejoong Song

    IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118

    CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0642 ,  H01L2027/11874

    Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.

    Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。

    Semiconductor devices and methods for manufacturing the same
    7.
    发明授权
    Semiconductor devices and methods for manufacturing the same 有权

    公开(公告)号：US10242984B2

    公开(公告)日：2019-03-26

    申请号：US15614911

    申请日：2017-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

    IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

    Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

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