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公开(公告)号:US11600340B2
公开(公告)日:2023-03-07
申请号:US17462298
申请日:2021-08-31
Inventor: Seungwoo Seo , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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公开(公告)号:US11544213B2
公开(公告)日:2023-01-03
申请号:US17369298
申请日:2021-07-07
Applicant: SAMSUNG ELECTRONICS CO., LTD. , SNU R&DB FOUNDATION
Inventor: Dongyoung Kim , Jung Ho Ahn , Sunjung Lee , Jaewan Choi
Abstract: A neural processor is provided. The neural processor includes a matrix device which is configured to generate an output feature map by processing a standard convolution operation and which has a systolic array architecture, and accelerators with an adder-tree structure which are configured to process depth-wise convolution operations for each of elements of the output feature map corresponding to lanes of the matrix device.
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公开(公告)号:USD992122S1
公开(公告)日:2023-07-11
申请号:US29779791
申请日:2021-04-21
Applicant: Samsung Electronics Co., Ltd.
Designer: Seokwon Bae , Jaewan Choi , Donghun Kim , Hankyung Ji , Doorae Kim
Abstract: FIG. 1 is a front perspective view of a wearable assistance robot showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top view thereof; and,
FIG. 7 is a bottom view thereof.-
公开(公告)号:US10242984B2
公开(公告)日:2019-03-26
申请号:US15614911
申请日:2017-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Panjae Park , Sutae Kim , Donghyun Kim , Ha-Young Kim , Jung-ho Do , Sunyoung Park , Sanghoon Baek , Jaewan Choi
IPC: H01L27/02 , H01L27/092 , H01L21/8238
Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.
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公开(公告)号:USD992741S1
公开(公告)日:2023-07-18
申请号:US29779793
申请日:2021-04-21
Applicant: Samsung Electronics Co., Ltd.
Designer: Seokwon Bae , Jaewan Choi , Donghun Kim , Hankyung Ji , Doorae Kim
Abstract: FIG. 1 is a front perspective view of a wearable assistance robot showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof; and,
FIG. 8 is another front perspective view thereof.
The broken lines in the figures depict portions of the wearable assistance robot that form no part of the claimed design.-
公开(公告)号:USRE49545E1
公开(公告)日:2023-06-06
申请号:US17175381
申请日:2021-02-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JinTae Kim , Jaewan Choi
IPC: H01L27/118 , H01L27/02
CPC classification number: H01L27/11807 , H01L27/0207 , H01L2027/11859 , H01L2027/11874 , H01L2027/11881 , H01L2027/11885
Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.
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公开(公告)号:US11436477B2
公开(公告)日:2022-09-06
申请号:US16857740
申请日:2020-04-24
Inventor: Yuhwan Ro , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号:USD1021862S1
公开(公告)日:2024-04-09
申请号:US29839378
申请日:2022-05-20
Applicant: Samsung Electronics Co., Ltd.
Designer: Jaehyuk Lee , Donghun Kim , Jooho Seo , Jaewan Choi
Abstract: FIG. 1 is a top perspective view of a wireless controller for internet of things, networks, and smart devices showing our new design;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is a bottom perspective view thereof.
The evenly-dashed broken lines in the drawings illustrate portions of the wireless controller for internet of things, networks, and smart devices that form no part of the claimed design.-
公开(公告)号:US11886985B2
公开(公告)日:2024-01-30
申请号:US17876136
申请日:2022-07-28
Inventor: Yuhwan Ro , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
CPC classification number: G06N3/063 , G06F9/3001 , G06F9/30145 , G06F9/3802 , G06F17/16 , G06N3/082 , G06N20/10
Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号:US11139033B2
公开(公告)日:2021-10-05
申请号:US16833864
申请日:2020-03-30
Inventor: Seungwoo Seo , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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